Pinned Repositories
1000base-x
1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)
32-bit-Multiplier-design-using-transistor-level-Digital-Gates
This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert
activecore
Hardware generation library based on "Kernel IP" (KIP) cores: programmable execution kernels inferred from microarchitectural templates
ADL
Architecture Description Language compiler for Orange C
alive2
Automatic verification of LLVM optimizations
amaranth
A modern hardware definition language and toolchain based on Python
arxiv-reference-graph
AUTOMATED-CIRCUIT-DESIGNER
“AUTOMATED CIRCUIT DESIGNER” can be used to design logic circuits. It reduces the Boolean expression & generate circuit diagram. It makes circuit construction easy & fast.
autowiring
Export an auto wiring build on circuit CAD to svg (Scalable Vector Graphics)
avr-ic-tester-v2
Chip tester
dingzex's Repositories
dingzex/autowiring
Export an auto wiring build on circuit CAD to svg (Scalable Vector Graphics)
dingzex/avr-ic-tester-v2
Chip tester
dingzex/cCompiler
c语言编译器，用 lex 和 yacc 工具完成词法分析与语法分析并生成语法树，C++实现了语 法树的解析并生成中间代码，生成中间代码的过程中实现了错误检测。C++实 现了中间代码的优化操作。之后利用 python 对中间代码进行处理并生成 mips 汇编码并且可以成功在 PCSpim（mips 模拟器）上运行。
dingzex/CHIP-hwtest
a little script to test chip hardware
dingzex/circuits-calculator
WIP POC of a circuit-calculation tool to work with 123DCircuits schematics's SVGs
dingzex/dragonegg
DragonEgg - GCC plugin Using LLVM
dingzex/eric
Git mirror of Eric Python IDE
dingzex/fossi
Candidate files for fossi-foundation libreChainEDA Tool Flow
dingzex/gdsplot
A simple stylesheet-based GDSII plotter
dingzex/GenLLVMDLLPy
A script to generate a DLL from LLVM .lib files generated by the default LLVM build.
dingzex/genovese
llvm backend mapper/router for multicontext dynamically reconfigureable architecture.
dingzex/gentoo-llvm
dingzex/Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
dingzex/libgds
A C library for reading and writing GDSII files
dingzex/llvm-cjg
An LLVM backend for my custom 32-bit RISC CPU https://scholarworks.rit.edu/theses/9550/
dingzex/llvm-general
Rich LLVM bindings for Haskell (with transfer of LLVM IR to and from C++, detailed compilation pass control, etc.)
dingzex/llvm-openisa
LLVM framework adapted to generate code for OpenISA
dingzex/LLVM-TableGen.tmBundle
LLVM TableGen syntax definition
dingzex/LLVMBasedAsmGenerator
Use LLVM's description of targets with td files to create HotSpot Assembler class for the same archs
dingzex/LogicCircuitDesign
For our 2016 C++ Final Project, we would like to create a circuit board interface, where the user has a menu of different gates, inputs, and wires. The user would build their own logic circuit design by dragging and dropping pieces on the interface and our program would build an expression representing that circuit. It would also calculate the output of a circuit depending on the values given by the inputs.
dingzex/lsi_cygwin
StarCore DSP IDE Tools modified under the GPL or the LGPL
dingzex/Native
Haxe LLVM code gen backend (not for Neko JIT)
dingzex/NISC
A single instruction set processor architecture
dingzex/pla-drawing
experiment: simple logic circuits as svg
dingzex/pyjaswd
Python based open-source jtag and swd debugger source. Currently supported by STM32F4-Discovery board as hardware debugger.
dingzex/PyTableGen
Python implementation of LLVM's TableGen
dingzex/smtdv
make your verilog DUT test more smart
dingzex/spgdb
StarCore DSP debugger tools modified under the GPL or the LGPL
dingzex/Switched-Multiported-RAM
Switched SRAM-based Multi-ported RAM
dingzex/tickysim
A timing based interconnection network simulator.