dlschmidt
Computer Science Student of the University of Erlangen and Working Student at Siemens Healthineers
Siemens HealthineersErlangen, Germany
dlschmidt's Stars
phdussud/pico-dirtyJtag
tvlad1234/linux-ch32v003
Linux on a $0.15 RISC-V microcontroller
zed-industries/zed
Code at the speed of thought – Zed is a high-performance, multiplayer code editor from the creators of Atom and Tree-sitter.
jawline/risc-v-emulator
A complete Risc-v RV32I emulator in Rust
tinygrad/tinygrad
You like pytorch? You like micrograd? You love tinygrad! ❤️
satya-das/cppparser
A library to parse C/C++ source as AST
prompt-toolkit/python-prompt-toolkit
Library for building powerful interactive command line applications in Python
ichi4096/vivado-on-silicon-mac
Installs Vivado on M1/M2 macs
efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
makslevental/openhls
PyTorch model to RTL flow for low latency inference
SymbioticEDA/riscv-formal
RISC-V Formal Verification Framework
AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
microsoft/vscode
Visual Studio Code
Architeuthis-Flux/Jumperless
A jumperless breadboard
Community-PIO-CH32V/platform-ch32v
PlatformIO platform for CH32V RISC-V chips (CH32V003, CH32V103, CH32V20x, CH32V30x, CH32X035) and CH56x, CH57x, CH58x, CH59x
pulp-platform/mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
riscv/riscv-opcodes
RISC-V Opcodes
UVVM/UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
quarbby/london-git
:train2: London Tube Map via a Git Network Graph
enjoy-digital/litex
Build your hardware, easily!
RTimothyEdwards/magic
Magic VLSI Layout Tool
vhdl-linter/vhdl-linter
mortenjc/systemverilog
Demonstrating systemverilog, verilator and google test for verification
enjoy-digital/litepcie
Small footprint and configurable PCIe core
microsoft/vscode-extension-samples
Sample code illustrating the VS Code extension API.
miguelsolorio/vscode-symbols
A file icon theme for VS Code
Jojodicus/recess
Runtime Error Checker for Exercises in SP using Shims
skeeto/endlessh
SSH tarpit that slowly sends an endless banner