donggyukim

Grad Student at UC Berkeley

@ucb-bar

Pinned Repositories

cacti
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
Language:C++0 1 01
ccbench
Memory System Microbenchmarks
Language:C00
chisel-tests
Chisel Experiments
Language:Scala01
cs152-sp18-lab4
Language:C1 1 02
CS281A
Language:TeX0 1 00
donggyukim.github.io
donggyukim.github.io
00
ec2-launch
Language:Python0 1 00
ee241b-project
EE241B Project by Donggyu Kim & Vighnesh Iyer
0 1 00
Marssx86
Language:C22
Speckle-2017
A wrapper for the SPEC CPU2017 benchmark suite.
Language:Shell6 1 03

donggyukim's Repositories

donggyukim/Speckle-2017
A wrapper for the SPEC CPU2017 benchmark suite.
Language:Shell6 1 03
donggyukim/Marssx86
Language:C22
donggyukim/cs152-sp18-lab4
Language:C1 1 02
donggyukim/cacti
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
Language:C++0 1 01
donggyukim/ccbench
Memory System Microbenchmarks
Language:C00
donggyukim/chisel-tests
Chisel Experiments
Language:Scala01
donggyukim/CS281A
Language:TeX0 1 00
donggyukim/donggyukim.github.io
donggyukim.github.io
00
donggyukim/ec2-launch
Language:Python0 1 00
donggyukim/ee241b-project
EE241B Project by Donggyu Kim & Vighnesh Iyer
0 1 00
donggyukim/esp-isa-sim
Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
Language:C1 0
donggyukim/mcpat
Automatically exported from code.google.com/p/mcpat
Language:C++1 0
donggyukim/riscv-fesvr
RISC-V Frontend Server
Language:C1 0
donggyukim/riscv-isa-sim
Spike, a RISC-V ISA Simulator
Language:C1 0
donggyukim/riscv-linux
Language:C1 02
donggyukim/riscv-pk
RISC-V Proxy Kernel
Language:C2