donggyukim's Stars
raysalemi/uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
vmware-archive/cascade
A Just-In-Time Compiler for Verilog from VMware Research
uclid-org/uclid
UCLID5: formal modeling, verification, and synthesis of computational systems
ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
SCons/scons
SCons - a software construction tool
scikit-learn/scikit-learn
scikit-learn: machine learning in Python
HewlettPackard/mcpat
An integrated power, area, and timing modeling framework for multicore and manycore architectures
HewlettPackard/cacti
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
azidar/firrtl-syntax
Vim syntax highlighting for Firrtl files
ccelio/Speckle
A wrapper for the SPEC CPU2006 benchmark suite.
awslabs/aws-fpga-app-notes
Application notes for the F1 EC2 Instance
aws/aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
ccelio/riscv-hpmcounters
A simple utility for doing RISC-V HPM perf monitoring.
ucb-bar/ccbench
Memory System Microbenchmarks
sifive/freedom
Source files for SiFive's Freedom platforms
ccelio/qsub-fpga
Infrastructure for managing FPGA cluster via qsub.
ccelio/initramfs_linux_flow
This is a hacky tool for building a BBL+Linux+InitRAMFS image for RISC-V.
riscvarchive/riscv-linux
RISC-V Linux Port
riscvarchive/riscv-fesvr
RISC-V Frontend Server
alperakcan/fuse-ext2
Fuse-ext2 is a multi OS FUSE module to mount ext2, ext3 and ext4 file system devices and/or images with read write support.
gem5/gem5
The official repository for the gem5 computer-system architecture simulator.
ucb-bar/riscv-sodor
educational microarchitectures for risc-v isa
riscv-software-src/riscv-tests
chipsalliance/rocket-chip
Rocket Chip Generator