Timer verification IP
Verification Hierarchy of Timer
This repository contains the verification IP of a Timer
Features of a Timer IP
- 64-bit timer with 12-bit prescaler and 8-bit step register
- Compliant with RISC-V privileged specification v1.11
- Configurable number of timers per hart and number of harts
Description
The timer module provides a configurable number of 64-bit counters where each counter increments by a step value whenever the prescaler times out. Each timer generates an interrupt if the counter reaches (or is above) a programmed value. The timer is intended to be used by the processors to check the current time relative to the reset or the system power-on.
Compatibility
The timer IP provides memory-mapped registers mtime and mtimecmp which can be used as the machine-mode timer registers defined in the RISC-V privileged spec. Additional features such as prescaler, step, and a configurable number of timers and harts have been added.
Features of a Timer verification IP
The verification IP is build on Universal verification methodology (UVM) that contain Constrained Random Testbenches
.
Working of verification IP
Note: Configuration of the timer is completely randomize by UVM testing environment for all internal registers of timer.
Configuration the timer
- Reset the Timer.
- First, verification IP generates randomized 64 bit
data
that configure theCOMPARE_REGISTERS
of timer to set the value that timer counts. - If
data
to be counted is less than or equal to64'h00000000FFFFFFFF
then set 32 bit registerCOMPARE_UPPER_REGISTER
to zero located at address0x110
, and also set 32 bit registerCOMPARE_LOWER_REGISTER
located at address0x10c
to value to be counted i.edata
. - If
data
to be counted is greater than64'h00000000FFFFFFFF
then set 32 bit registersCOMPARE_UPPER_REGISTER
&COMPARE_LOWER_REGISTER
to upper 32 bits ofdata
and lower 32 bits ofdata
located at0x110
&0x10c
respectively. - Randomize prescale bits and step bits in the register
CFG0
located at address0x100
. - Enable interrupt by setting zeroth bit of register
INTR_ENABLE0
located at address0x114
. - Verification IP calculates and predicts the number of clock cycles required to complete the counting. The prediction of clock cycle is calculated depening on prescale and step assigned in register
0x100
as mentioned in point 4.
Activation the timer
- Acticate the timer by setting zeroth bit of register
ALERT_TEST
located at address0x0
.
Result
- Waits until
intr_timer_expired_0_0_o
signal is enabled from the DUT (timer), that indicates timer has compeletd the counting. - Compare the number of clock cycles after which
intr_timer_expired_0_0_o
signal is enabled with the predicted clock cycle calculated before (mentioned in point 7). - If comparison is succussful then contrained random UVM test is
PASSED
.
How to run the verification IP?
Clone respositaries common_peripheral_ip and common_peripheral_vips that contain IP and verification IP respectively. Clone the mentioned repositories parallel to each other using following couple of commands
git clone https://github.com/merledu/common_peripheral_ips.git
git clone https://github.com/AuringzaibSabir/timer_verification_ip.git
For running verification IP with different number of contraint random test
Redirect to the following path
to test the timer
cd timer_verification_ip/timer/
Excecute the command
python run_test.py < enter number of test to run >
python run_test.py 100
In above command 100
means 100 constraint random test will be generated.
Note you can observe the test results in test_result.txt
file
OR
Can also run the single test by following steps
Redirect to the following path
to test the timer
cd timer_verification_ip/timer/
Excecute the command
./command