doudouli12

AHB-SRAMC

IC Verification & SV Demo

AHB-to-APB-Bridge-Verification

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

ahb2apb-bridge

An uvm verification env for ahb2apb bridge

ahb_sramc

ahb scram controller, design and verification

ALU-Verification-Environment

Development UVM Verification Environment for ALU DUT

alu_tb

Basic ALU testbench written in UVM for experiments

ALU_Verification_IP

Verification IP for ALU written using SystemVerilog (UVM)

AMBA_APB_SRAM

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

apb_vip

Verification IP for APB protocol

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

doudouli12/AHB-SRAMC

IC Verification & SV Demo

doudouli12/AHB-to-APB-Bridge-Verification

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

doudouli12/ahb2apb-bridge

An uvm verification env for ahb2apb bridge

doudouli12/ALU-Verification-Environment

Development UVM Verification Environment for ALU DUT

doudouli12/apb_vip

Verification IP for APB protocol

doudouli12/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

doudouli12/axi4_vip

Verification IP for APB protocol

doudouli12/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

doudouli12/cpu8080-alu

UVM code to verify ALU

doudouli12/FIFO_verification-

fifo verification IP using system verilog

doudouli12/i2c_vip

Verification IP for I2C protocol

doudouli12/LM-RISCV-DV

An Open-Source Design and Verification Environment for RISC-V

doudouli12/MPSoC-DV

MPSoC verified with UVM/OSVVM/FV

doudouli12/opentitan

OpenTitan: Open source silicon root of trust

doudouli12/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

doudouli12/riscv

RISC-V CPU Core (RV32IM)

doudouli12/riscv-formal

RISC-V Formal Verification Framework

doudouli12/riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

doudouli12/SM3_core

doudouli12/SoC-DV

System on Chip verified with UVM/OSVVM/FV

doudouli12/SPI-Interface

UVM Testbench to verify serial transmission of data between SPI master and slave

doudouli12/spi_vip

Verification IP for SPI protocol

doudouli12/timer_verification_ip

This repository contains a Verification IP for the timer. This VIP tests the timer by applying constrained random stimulus. Sequences of transactions reset, configure the timer, and perform read & write operations on the respective registers of the timer.

doudouli12/uart2bustestbench

UVM Verification IP to uart2bus IP.

doudouli12/uart_vip

Verification IP for UART protocol

doudouli12/uvm_tb_cross_bar

SystemVerilog UVM testbench example

doudouli12/Verification_ARPS_IP_project

doudouli12/verilog-axi

Verilog AXI components for FPGA implementation

doudouli12/wbuart32

A simple, basic, formally verified UART controller

doudouli12/wujian100_open

IC design and development should be faster，simpler and more reliable