Pinned Repositories
AHB-SRAMC
IC Verification & SV Demo
AHB-to-APB-Bridge-Verification
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
ahb2apb-bridge
An uvm verification env for ahb2apb bridge
ahb_sramc
ahb scram controller, design and verification
ALU-Verification-Environment
Development UVM Verification Environment for ALU DUT
alu_tb
Basic ALU testbench written in UVM for experiments
ALU_Verification_IP
Verification IP for ALU written using SystemVerilog (UVM)
AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
apb_vip
Verification IP for APB protocol
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
doudouli12's Repositories
doudouli12/ahb_sramc
ahb scram controller, design and verification
doudouli12/alu_tb
Basic ALU testbench written in UVM for experiments
doudouli12/ALU_Verification_IP
Verification IP for ALU written using SystemVerilog (UVM)
doudouli12/AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
doudouli12/fpga-support
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
doudouli12/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
doudouli12/pulpino_soc_uvm_testbench
UVM testbench for verifying the Pulpino SoC
doudouli12/RISC_VERIF_DEMO_0
a very simple risc_cpu verification demo with uvm
doudouli12/Single-Cycle-Processor
Single-Cycle RISC-V Processor in systemverylog
doudouli12/SPI-Interface
UVM Testbench to verify serial transmission of data between SPI master and slave
doudouli12/spi_vip
Verification IP for SPI protocol
doudouli12/UART
UART design in SV and verification using UVM and SV
doudouli12/uart_vip
Verification IP for UART protocol
doudouli12/uvm-alu
ALU verification using UVM
doudouli12/UVM-APB_RAL
This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
doudouli12/UVM-Verification-IP-for-switch
A complete UVM verification IP for simple switch (router)