emruiz

emruiz's Stars

• mrphrazer/reverser_ai

  Provides automated reverse engineering assistance through the use of local large language models (LLMs) on consumer hardware.

  Language:Python78443

• dnakov/r2d2

  🤖🏴‍☠️ radare2 plugin for GPT-4 🦜. Solve crackmes automatically 🪄

  Language:Python26215

• slaclab/ruckus

  Vivado build system

  Language:Tcl6833

• intel/rohd-hcl

  A hardware component library developed with ROHD.

  Language:Dart7919

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog46896

• chipsalliance/VeeRwolf

  FuseSoC-based SoC for VeeR EH1 and EL2

  Language:Verilog27764

• exaloop/codon

  A high-performance, zero-overhead, extensible Python compiler using LLVM

  Language:C++14.3k501

• lucas-schuermann/ten-minute-physics-rs

  Reimplementation of Matthias Müller's "Ten Minute Physics" demos in Rust with WASM + WebGL

  Language:Rust1376

• stevehoover/LF-Building-a-RISC-V-CPU-Core

  Language:TL-Verilog329177

• openhwgroup/cv32e40s

  4 stage, in-order, secure RISC-V core based on the CV32E40P

  Language:SystemVerilog12621

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.2k673

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog924410

• google/gf180mcu-pdk

  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

  Language:Makefile35854

• lapce/lapce

  Lightning-fast and Powerful Code Editor written in Rust

  Language:Rust34.2k1k

• dineshannayya/riscduino

  Arduino compatible Risc-V Based SOC

  Language:Tcl13122

• MoonbaseOtago/vroom

  VRoom! RISC-V CPU

  Language:Verilog46921

• luker983/nsa-codebreaker-2021

  NSA Codebreaker Challenge 2021 Write-Ups

  Language:C546

• numato/samplecode

  This repository contains sample code for different Numato Lab products

  Language:C132339

• samehattia/StateLink

  StateLink is a debugging framework that allows a design-under-test to run with full visibility in a simulator and to interact with on-board I/Os and other system parts that run on an FPGA.

  Language:C++31

• slaclab/surf

  A huge VHDL library for FPGA development

  Language:VHDL32056

• fusesoc/tiny-cores

  Collection of assorted small cores

  Language:Verilog113

• fusesoc/fusesoc-cores

  FuseSoC standard core library

  10529

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1k252

• bespoke-silicon-group/basejump_stl

  BaseJump STL: A Standard Template Library for SystemVerilog

  Language:SystemVerilog49797

• jameslzhu/riscv-card

  An unofficial assembly reference for RISC-V.

  Language:TeX44556

• chipsalliance/rocket-chip

  Rocket Chip Generator

  Language:Scala3.2k1.1k

• SpinalHDL/VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  Language:Assembly2.4k407

• olofk/fusesoc

  Package manager and build abstraction tool for FPGA/ASIC development

  Language:Python1.2k242

• olofk/corescore

  CoreScore

  Language:Verilog13440

• olofk/observer

  Language:Verilog403