Issues
- 5
Race all sorts of roms
#204 opened by ogamespec - 0
Update design
#283 opened by ogamespec - 7
- 11
Test the cc check circuit
#266 opened by ogamespec - 1
Check CLK7 usage
#274 opened by ogamespec - 10
Value of registers are stored inverted.
#240 opened by Rodrigodd - 12
CPU never writes to external bus
#239 opened by Rodrigodd - 0
- 10
Verify ALU
#229 opened by ogamespec - 36
`CLK_ENA` should only go high after `OSC_STABLE`
#219 opened by Rodrigodd - 1
Verify CLK trees
#226 opened by ogamespec - 0
Use Gekkio names
#214 opened by ogamespec - 0
Rename LoadIR port -> M1
#211 opened by ogamespec - 1
Crosscheck with @gekkio
#141 opened by ogamespec - 2
PC does not increment after executing NOP
#171 opened by ogamespec - 0
Double check decoder trees
#117 opened by ogamespec - 6
HDL Solidification
#142 opened by ogamespec - 0
WTF with DataLatch
#153 opened by ogamespec - 2
Check the behavior of memory items with the edge
#140 opened by ogamespec - 0
Bottom HDL
#95 opened by ogamespec - 1
I don't understand what it wants (AddrBus)
#138 opened by ogamespec - 0
Seq.v does not synthesize due to declaration order
#134 opened by SonoSooS - 0
- 0
- 0
Simulate Decoder
#96 opened by ogamespec - 0
Decoders HDL
#94 opened by ogamespec - 0
Refine Bottom Topo
#93 opened by ogamespec - 0
Refine ALU Topo
#92 opened by ogamespec - 1