epfl-vlsc/bitfiltrator
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
PythonMIT
Issues
- 4
Can we use this approach for other FPGAs?
#4 opened by akshar001 - 5
can't generate parts_webpack.json
#3 opened by ghyghy123 - 1
take 2 positional argument but 3 were given
#1 opened by HankIC - 8
could not create empty bitstream
#2 opened by ghyghy123