eric900115

eric900115's Stars

• jmluu/Awesome-Efficient-Training

  A collection of research papers on efficient training of DNNs

  687

• MPSLab-ASU/ML-Accelerators

  Topics in Machine Learning Accelerator Design

  4912

• ucb-ee290c/sp21-dma

  EE290C DMA

  Language:Scala7

• chunzhimu/Verilog-HDL

  things about Verilog hardware description language

  Language:Verilog126

• kaitoukito/Computer-Science-Textbooks

  Collect some CS textbooks for learning.

  536149

• dumpo/digital_IC_design_notes

  数字IC设计 学习笔记

  11126

• LeiWang1999/FPGA

  帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

  3.9k657

• ucb-bar/constellation

  A Chisel RTL generator for network-on-chip interconnects

  Language:Scala16924

• KyleParkJong/Network-on-Chip-Simulator

  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator

  Language:Verilog15

• kippy620/uvm

  Learning uvm step by step.

  Language:SystemVerilog6

• sin-x/FPGA

  数字IC相关资料

  930280

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.5k586

• nvdla/vp

  Virtual Platform for NVDLA

  Language:C++13681

• wewe5215/NTHU_Logic_Design_Lab_2022

  Language:Verilog2

• ucb-bar/chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  Language:Scala1.6k628

• ics-jku/riscv-vp-plusplus

  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.

  Language:C++234

• yuyuranium/FPGA-Project-2022-simple-tpu

  Systolic array based simple TPU for CNN on PYNQ-Z2

  Language:Jupyter Notebook182

• erhwenkuo/deep-learning-with-keras-notebooks

  Jupyter notebooks for using & learning Keras

  Language:Jupyter Notebook2.2k686

• ntampouratzis/FPGA-based-LSTM

  A novel FPGA-based intent recognition systemutilizing deep recurrent neural networks

  Language:C++225

• walkieq/RNN_HLS

  An LSTM template and a few examples using Vivado HLS

  Language:C3911

• lydiawunan/HLS-Perf-Prediction-with-GNNs

  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing

  446

• FedericoSerafini/HLS-CNN

  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

  Language:C287

• basicmi/AI-Chip

  A list of ICs and IPs for AI, Machine Learning and Deep Learning.

  Language:PHP1.6k273

• Xilinx/SDAccel_Examples

  SDAccel Examples

  Language:C++354211

• sharc-lab/FPGA_ECE8893

  Language:C++2826

• diwu1990/uSystolic-Sim

  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

  Language:C++6114

• joao-borrego/hw_sw

  Hardware Software Co-Design Course Project

  Language:C32

• guru-irl/parallel-aes

  Parallel implementation of the Advanced Encryption Standard.

  Language:C++94

• NTU-CSIE-HLS/ACA-HLS

  Advanced Computer Architecture with High-Level-Synthesis [2021 Spring]

  Language:C5

• ykqiu/image-processing

  Real-Time Image Processing for ASIC/FGPA

  Language:Verilog74