fanfancy

fanfancy's Stars

• jiangwx/SkrSkr

  The second place winner for DAC-SDC 2020

  Language:Tcl9626

• peng-zhihui/Dummy-Robot

  我的超迷你机械臂机器人项目。

  Language:C11.7k2.6k

• fastmachinelearning/hls4ml-tutorial

  Tutorial notebooks for hls4ml

  Language:Jupyter Notebook275123

• fastmachinelearning/hls4ml

  Machine learning on FPGAs using HLS

  Language:C++1.2k389

• thesps/conifer

  Fast inference of Boosted Decision Trees in FPGAs

  Language:Python4323

• sjtug/SJTUBeamer

  上海交通大学 Beamer 模版 | Beamer template for Shanghai Jiao Tong University

  Language:TeX55060

• aserenate/gem5_gt

  Language:C++1

• fanfancy/gem5_gt

  Language:C++2

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k999

• arasi15/CNN-Accelerator-Implementation-based-on-Eyerissv2

  Language:Verilog769

• svzj95/gem5_gt

  Language:C++14

• pkuzjx/EDA-wiki

  EDA wiki

  Language:Shell11327

• accel-sim/accel-sim-framework

  This is the top-level repository for the Accel-Sim framework.

  Language:Python267104

• peng-zhihui/PocketLCD

  带充电宝功能的便携显示器

  6.1k1k

• astra-sim/astra-sim

  ASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scale

  Language:C++21790

• jgoeders/dac_sdc_2020_designs

  Designs for finalist teams of the DAC System Design Contest

  Language:Objective-C3419

• msr-fiddle/pipedream

  Language:Python371113

• astra-sim/astra-network-garnet

  gem5 version for garnet network backend for ASTRA-sim (http://github.com/astra-sim/astra-sim)

  Language:C++73

• ARM-software/SCALE-Sim

  Language:Python321148

• open-mmlab/mmdetection

  OpenMMLab Detection Toolbox and Benchmark

  Language:Python28.6k9.3k

• BRTResearch/AIChip_Paper_List

  547111

• gem5/gem5

  The official repository for the gem5 computer-system architecture simulator.

  Language:C++1.5k1.1k

• booksim/booksim2

  BookSim 2.0

  Language:C++245158

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.5k344

• dpretet/async_fifo

  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

  Language:Verilog22770

• davidepatti/noxim

  Network on Chip Simulator

  Language:C++216117

• KastnerRG/riffa

  The RIFFA development repository

  Language:Verilog737308

• microsoft/nni

  An open source AutoML toolkit for automate machine learning lifecycle, including feature engineering, neural architecture search, model compression and hyper-parameter tuning.

  Language:Python13.9k1.8k

• fanfancy/caffe_ssd_compression

  Caffe: a fast open framework for deep learning.

  Language:C++1

• fzliu/style-transfer

  An implementation of "A Neural Algorithm of Artistic Style" by L. Gatys, A. Ecker, and M. Bethge. http://arxiv.org/abs/1508.06576.

  Language:Python1.5k388