/EE2026-FPGA

EE2026 Digital Design FPGA Project

Primary LanguageVerilog

EE2026 Digital Design FPGA Project

A Sight and Souch Entertainment (SSE) system for our FPGA Design Project as first year computer engineering undergraduates. Written in Verilog HDL for the Basys3 Artix-7 FPGA board.

Hardware Requirements

  • Digilent Pmod 96x64 pixel RGB OLED
  • Digilent Pmod Mic 3

Development Environment

  • Vivado® Design Suite 2018.2 - HLx Edition

Project Report

S1_19_Sun Jiale_SWAMINATHAN VARUN_Report