flyjancy

Pinned Repositories

common_cells
common verilog components
Language:Verilog7 1 00
CortexM0_SoC
Cortex M0 based SoC
Language:C70 4 028
CortexM0_SoC_Task
Step by step tutorial for building CortexM0 SoC
Language:Verilog36 3 08
flyjancy
My Profile
10
hdlbits_solution
Language:Verilog1 1 00
notes
Language:Shell0 1 00
Reindeer_Step
Reindeer Soft CPU for Step CYC10 FPGA board
Language:Verilog0 0 00
reliability-paper
10
report
my latex template
Language:TeX2 1 01
SpinalHDLCode
Code when studying SpinalHDL
Language:Scala1 1 00

flyjancy's Repositories

flyjancy/CortexM0_SoC
Cortex M0 based SoC
Language:C70 4 028
flyjancy/CortexM0_SoC_Task
Step by step tutorial for building CortexM0 SoC
Language:Verilog36 3 08
flyjancy/common_cells
common verilog components
Language:Verilog7 1 00
flyjancy/report
my latex template
Language:TeX2 1 01
flyjancy/flyjancy
My Profile
10
flyjancy/hdlbits_solution
Language:Verilog1 1 00
flyjancy/reliability-paper
10
flyjancy/SpinalHDLCode
Code when studying SpinalHDL
Language:Scala1 1 00
flyjancy/notes
Language:Shell0 1 00
flyjancy/Reindeer_Step
Reindeer Soft CPU for Step CYC10 FPGA board
Language:Verilog0 0 00