Pinned Repositories
arov
axi_hls_tg
AXI HLS Traffic Generator
dummy_vip
Files for the IP Integration Exercise
fullstack_ip_integration
gbellocchi.github.io
genov
hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
hwpe-ctrl
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
hwpe-gen-app
hwpe-stream
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
gbellocchi's Repositories
gbellocchi/arov
gbellocchi/axi_hls_tg
AXI HLS Traffic Generator
gbellocchi/dummy_vip
Files for the IP Integration Exercise
gbellocchi/fullstack_ip_integration
gbellocchi/gbellocchi.github.io
gbellocchi/genov
gbellocchi/hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
gbellocchi/hwpe-ctrl
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
gbellocchi/hwpe-gen-app
gbellocchi/hwpe-stream
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
gbellocchi/hwpe-tb
Template testbench for HWPEs (using the hwpe-mac-engine as example)
gbellocchi/pulp_soc
gbellocchi/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
gbellocchi/pulpissimo-zcu102
Implementation of a 32-bit single core risc-v platfrom for Xilinx zcu102 board
gbellocchi/richie-docs
gbellocchi/svprettyplot
gbellocchi/xil_open_hw_23
GenOv: Streamlining the Design and Optimization of Heterogeneous RISC-V-based FPGA Overlays