gilgamsh's Stars
krahets/hello-algo
《Hello 算法》:动画图解、一键运行的数据结构与算法教程。支持 Python, Java, C++, C, C#, JS, Go, Swift, Rust, Ruby, Kotlin, TS, Dart 代码。简体版和繁体版同步更新,English version ongoing
vllm-project/vllm
A high-throughput and memory-efficient inference and serving engine for LLMs
llvm/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
mli/paper-reading
深度学习经典、新论文逐段精读
HigherOrderCO/Bend
A massively parallel, high-level programming language
Dao-AILab/flash-attention
Fast and memory-efficient exact attention
dabeaz-course/python-mastery
Advanced Python Mastery (course by @dabeaz)
HigherOrderCO/HVM
A massively parallel, optimal functional runtime in Rust
dabeaz-course/practical-python
Practical Python Programming (course by @dabeaz)
bayesian-optimization/BayesianOptimization
A Python implementation of global optimization with gaussian processes.
gpu-mode/lectures
Material for gpu-mode lectures
banach-space/llvm-tutor
A collection of out-of-tree LLVM passes for teaching and learning
benedekrozemberczki/awesome-community-detection
A curated list of community detection research papers with implementations.
dofy/learn-vim
Learning Vim. A Hands-On Tutorial of Vim.
tshort/dactyl-keyboard
Dactyl-ManuForm, a parameterized ergonomic keyboard
buddy-compiler/buddy-mlir
An MLIR-based compiler framework bridges DSLs (domain-specific languages) to DSAs (domain-specific architectures).
saebyn/munkres-cpp
Kuhn-Munkres (Hungarian) Algorithm in C++
Limeoats/BigNumber
C++ class for creating and computing arbitrary-length integers
EachSheep/ShortcutsBench
ShortcutsBench: A Large-Scale Real-World Benchmark for API-Based Agents
rachelselinar/DREAMPlaceFPGA
An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
NVlabs/CircuitOps
liyanqing1987/libertyParser
liberty parser (For parsing IC timing lib file)
hkust-zhiyao/MasterRTL
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Centre-for-Hardware-Security/asap7_reference_design
reference block design for the ASAP7nm library in Cadence Innovus
rachelselinar/ReGDS-Logic-Gate-Extraction
A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
yaoxufeng/RTLRewriter-Bench
eclufsc/libertyParser
Mirror of Synopsys's Liberty parser library
jkim971201/SkyPlace
ABKGroup/DG-RePlAce
GPU-accelerated RePlAce
zhilix/DREAMPlaceFPGA-MP
DREAMPlaceFPGA for MLCAD23 contest