google/xls

yosys report syntax error for the array expression codegen_main generates

Closed this issue · 3 comments

Aaronchan-sz commented

Yosys reports:

1. Executing Verilog-2005 frontend: test.v
test.v:5: ERROR: syntax error, unexpected invalid token

This is test.v, generated from ./xls-v0.0.0-5603-g3aadb2f6c-linux-x64/codegen_main -generator=combinational test.opt.ir > test.v

module __test__test_main(
  input wire [1:0] idx,
  output wire [2:0] out
);
  wire [2:0] ma[4] = '{3'h1, 3'h2, 3'h3, 3'h4};

  assign out = ma[idx];
endmodule

To Reproduce
test.x source DSLX file:

fn test_main(idx:u2)-> u3  {
    let ma:u3[4] = [u3:1, u3:2, u3:3, u3:4];

    ma[idx]
}

After ir_converter_main, ./xls-v0.0.0-5603-g3aadb2f6c-linux-x64/ir_converter_main test.x > test.ir

package test

file_number 0 "test.x"

fn __test__test_main(idx: bits[2]) -> bits[3] {
  literal.2: bits[3] = literal(value=1, id=2, pos=[(0,1,20)])
  literal.3: bits[3] = literal(value=2, id=3, pos=[(0,1,26)])
  literal.4: bits[3] = literal(value=3, id=4, pos=[(0,1,32)])
  literal.5: bits[3] = literal(value=4, id=5, pos=[(0,1,38)])
  ma: bits[3][4] = array(literal.2, literal.3, literal.4, literal.5, id=6, pos=[(0,1,19)])
  ret array_index.7: bits[3] = array_index(ma, indices=[idx], id=7, pos=[(0,3,6)])
}

Afte opt_main, ./xls-v0.0.0-5603-g3aadb2f6c-linux-x64/opt_main --top=__test__test_main test.ir > test.opt.ir

package test

file_number 0 "test.x"

top fn __test__test_main(idx: bits[2]) -> bits[3] {
  ma: bits[3][4] = literal(value=[1, 2, 3, 4], id=8, pos=[(0,1,19)])
  ret array_index.7: bits[3] = array_index(ma, indices=[idx], id=7, pos=[(0,3,6)])
}
mikex-oss commented

To repro, you'll need to provide the codegen options, but it would appear from the array assignment pattern that you are asking XLS to generate SystemVerilog.

Your Yosys error says "Executing Verilog-2005 frontend" which wouldn't support this type of assignment.

  • 👍1
Aaronchan-sz commented

To repro, you'll need to provide the codegen options, but it would appear from the array assignment pattern that you are asking XLS to generate SystemVerilog.

Your Yosys error says "Executing Verilog-2005 frontend" which wouldn't support this type of assignment.

Updated.

mikex-oss commented

SystemVerilog is the default. You need to turn if off if you're going to use the generated code with a Verilog-2005 compiler.

https://google.github.io/xls/codegen_options/#codegen-mapping

--use_system_verilog sets if the output should use SystemVerilog constructs such as SystemVerilog array assignments, @always_comb, @always_ff, asserts, covers, etc. True by default.

  • 👍1