gtaylormb

gtaylormb's Stars

• secworks/md5

  Hardware implementation of the hash function md5

  Language:Verilog63

• mbuesch/crcgen

  Generator for CRC HDL code (VHDL, Verilog, MyHDL)

  Language:Python277

• rggen/rggen

  Code generation tool for control and status registers

  Language:Ruby31943

• AndrewNolte/vscode-system-verilog

  HDL support for VS Code

  Language:TypeScript121

• MikePopoloski/slang

  SystemVerilog compiler and language services

  Language:C++595132

• gtaylormb/opl3_fpga

  Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

  Language:VHDL36142

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.7k410

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.4k872

• chili-chips-ba/openCologne

  Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

  Language:Verilog402

• nukeykt/Nuked-OPL3

  Highly accurate Yamaha OPL3 (YMF262, CT1747) emulator

  Language:C16618

• theypsilon/Update_All_MiSTer

  All-in-one script for updating your MiSTer

  Language:Python66428

• raetro/sdk-docker-fpga

  Intel Quartus Prime Synthesis Engine for Docker

  Language:Dockerfile439

• hypernyan/eth_vlg

  Language:SystemVerilog5117

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.8k522

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.5k590

• cocotb/cocotb-bus

  Pre-packaged testbenching tools and reusable bus interfaces for cocotb

  Language:Python5639

• zerkman/demomachine

  Simple architecture to make demos on a FPGA

  Language:VHDL10

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.8k505

• Saanlima/Pipistrello

  Pipistrello FPGA board by Saanlima Electronics

  Language:Verilog83

• skiphansen/panog2_opl3

  Yamaha OPL3 for the second generation Panologic thin client

  Language:C7

• shakemid/pcsensor-temper

  PCSensor / TEMPer driver for Linux/Solaris

  Language:C387

• skiphansen/pano_hello_g1

  Simple "Hello World" base project for Pano Logic G1

  Language:Verilog5

• skiphansen/panog1_opl3

  A port of the OPL3 to the Panologic G1 thin client

  Language:Verilog184

• ATaylorCEngFIET/Ultra96V2_DisplayPort

  Bare Metal Display Port Example for the Ultra96 V2

  Language:VHDL93

• MiSTer-devel/ao486_MiSTer

  ao486 port for MiSTer

  Language:Verilog26269

• jamieiles/80x86

  80186 compatible SystemVerilog CPU core and FPGA reference design

  Language:C++37251

• schlae/adlib

  Reproduction AdLib Sound Card, OPL2, Circa 1990

  14727

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k688

• waltervn/wjp-dosbox

  Import of DOSBox with git-svn. Not necessarily up-to-date. Also contains a branch with idados support.

  Language:C++33

• knewron-technologies/1btn

  1btn (one button) uses the internet to complete a task with the simple, satisfying click of a single button. It connects to the internet over Wi-Fi to trigger whatever action you have assigned to it using a simple, online interface. One click, one task. It’s that simple. Unlike many other “Internet of Things” devices, 1btn does not maintain a continuous connection to the internet. Instead, it sleeps until it is pressed, then it connects to the internet, performs the assigned task, tells you the outcome via its multi-colored LEDs, and then returns to rest.

  Language:Lua12317