habibagamal/RISC-V-Implementation
This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers
Verilog
This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers
Verilog