habibagamal

OGRE

Global Router Built for ICCAD Contest 2019

Cache-Simulation

This application is a cache simulation (Direct mapped, fully associative and set associative)

Hauffman-Coding-

This program compresses and decompresses ASCII-encoded text files using Hauffman Encoding

MLUtilityApp-Django

Loan Status Prediction using Python and Django

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

RISC-V-Implementation

This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers

RISC-V-RV32I-simulation

C++ simulation of RISC-V RV32I

SoC_Automation

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

Distributed

Snapchat-like-Application

Computer Vision course final project.

habibagamal/SoC_Automation

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

habibagamal/RISC-V-Implementation

This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers

habibagamal/Cache-Simulation

This application is a cache simulation (Direct mapped, fully associative and set associative)

habibagamal/Hauffman-Coding-

This program compresses and decompresses ASCII-encoded text files using Hauffman Encoding

habibagamal/openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

habibagamal/RISC-V-RV32I-simulation

C++ simulation of RISC-V RV32I

habibagamal/VCDtoWaveform-Viewer

habibagamal/Verilog-Digital-Alarm-Clock

A Verilog implementation of a digital clock with a stopwatch and alarm.

habibagamal/MLUtilityApp-Django

Loan Status Prediction using Python and Django

habibagamal/Andrew-NG-Deep-learning-course-on-coursera

This is my implelementation of the programming assignments for the specialization of deep learning on coursera by Andrew NG. https://www.coursera.org/specializations/deep-learning?

habibagamal/Android_Calculator

A simple calculator implemented to run on the Android Platform (Android 4.4 (Kitkat))

habibagamal/BankingWebApp-w-interface

SQL database project. Implemented with html, css, bootstrap, php.

habibagamal/DeepLearning

This folder includes jupyter notebook files to some of the things I learnt and tutorials I followed for my Summer 2019 Internship

habibagamal/Draw-the-line

A graph plotter that works with any pdf containing one (or more) graphs :chart_with_upwards_trend:

habibagamal/DSP_DFT_IDFT_Ass2

Python Implementation of Discrete Fourier Transform

habibagamal/EmbeddedProject_HeartMonitor

Heart Monitor

habibagamal/FFT-implementation

Python implementation of Fast Fourier Tranform

habibagamal/filterer

My first mobile application. A photo editor app!

habibagamal/MongoDB

mongodb facebook like application without interface

habibagamal/opencv

Open Source Computer Vision Library

habibagamal/soukUp

DD2 mini-project

habibagamal/Tomasulo-s-Simulation

C++ simulation of Tomasulo's Algorithm

habibagamal/tutorials

habibagamal/UNIX-shell

implementation of UNIX shell. Operating Systems Assignment 5.

habibagamal/VCD2Waveform

This program takes a verilog vcd file and outputs the waveforms using wavedrome. The input is the name of the vcd file & the name of the output file. The output is an HTML file.