hfuttcy

hfuttcy's Stars

• Enanter/ADPLL

  All Digital Phase-Locked Loop

  Language:Tcl8

• filipamator/adpll

  All digital PLL

  Language:VHDL245

• igorauad/digital_pll

  MATLAB Implementation of a Digital PLL

  Language:Matlab148

• jammychiou1/CDR_simulation

  Basic Clock Data Recovery circuit simulation and experimentation with Python.

  Language:Python3

• rishabh-jain97/Clock_Data_Recovery

  A circuit for clock-data-recovery via a Serdes lane. Made in cooperation with Nicholas DiPaolo (lab partner) for ELEC 4706

  Language:VHDL72

• redchenjs/clock_data_recovery_max10

  Clock Data Recovery | 時鐘數據恢復

  Language:Verilog101

• ZipCPU/dpll

  A collection of phase locked loop (PLL) related projects

  Language:Verilog9926

• mathworks/MATLAB-Simulink-Challenge-Project-Hub

  This MATLAB and Simulink Challenge Project Hub contains a list of research and design project ideas. These projects will help you gain practical experience and insight into technology trends and industry directions.

  Language:MATLAB1.3k283

• lulf0020/Behavior-modeling-of-PLL

  MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/

  Language:MATLAB7

• SparcLab/OpenSERDES

  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

  Language:Verilog14330

• wesm/pydata-book

  Materials and IPython notebooks for "Python for Data Analysis" by Wes McKinney, published by O'Reilly Media

  Language:Jupyter Notebook22.3k15.2k

• SPISim/ML_CtleModeling

  Use machine learning/data science techniques to model SERDES's CTLE

  Language:Jupyter Notebook84

• labolas89/cpp_serdes

  Language:C++3

• richard259/serdespy

  Python library for SerDes modelling

  Language:Python5726

• muhammadaldacher/Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp

  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.

  288

• fyyaz/dfe_adaptation

  python simulation of DFE adaptation using LMS algorithm to cancel post cursor ISI from channel

  Language:Python11

• brown9804/PCIe_physical_layer

  Implementation of the PCIe physical layer

  Language:Verilog3010

• kangjian888/PAM4-RGB-FPGA

  Language:SystemVerilog3

• M-HHH/HDLBits_Practice_verilog

  This is a practice of verilog coding

  Language:Verilog308

• tsaoalbert/openroad

  Language:Verilog1

• d2l-ai/d2l-zh

  《动手学深度学习》：面向中文读者、能运行、可讨论。中英文版被70多个国家的500多所大学用于教学。

  Language:Python63.9k11.1k

• bayandin/awesome-awesomeness

  A curated list of awesome awesomeness

  Language:Ruby32.1k3.6k

• oatpp/oatpp

  🌱Light and powerful C++ web framework for highly scalable and resource-efficient web application. It's zero-dependency and easy-portable.

  Language:C++7.9k1.3k

• Alinshans/MyTinySTL

  Achieve a tiny STL in C++11

  Language:C++11.5k3.3k

• EZLippi/Tinyhttpd

  Tinyhttpd 是J. David Blackstone在1999年写的一个不到 500 行的超轻量型 Http Server，用来学习非常不错，可以帮助我们真正理解服务器程序的本质。官网:http://tinyhttpd.sourceforge.net

  Language:C11.4k3.9k

• cbsheng/tinyhttpd

  tinyhttpd的详细注释版，十分适合入门者学习的一个项目

  Language:C1.7k557

• stevelorenz/build-vnf

  :coffee: Experimental/research project to build high-performance and energy-efficient virtual network functions (VNFs).

  Language:C395

• JiYou/openstack

  《OpenStack开源云王者归来》

  Language:Python408310

• alibaba/Alibaba-MIT-Speech

  Alibaba speech technology

  913251

• RasaHQ/rasa

  💬 Open source machine learning framework to automate text- and voice-based conversations: NLU, dialogue management, connect to Slack, Facebook, and more - Create chatbots and voice assistants

  Language:Python19k4.6k