hkust-zhiyao

Pinned Repositories

AgileDevelop
AgileDevelop&AgileTransfer: Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies
Language:Python3 1 00
APPLE
A circuit-element level explainer to explain machine learning model's prediction on chip layouts.
Language:Python17 1 00
AssertLLM
Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Language:Verilog16 1 02
MasterRTL
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Language:Verilog28 3 123
PANDA
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
Language:Python11 2 00
RTL-Coder
A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
Language:Python114 5 1315
RTL-Timer
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Language:Verilog15 2 10
RTLLM
An open-source benchmark for generating design RTL with natural language
Language:Verilog59 2 613
SpecLLM
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Language:Verilog8 0 01

hkust-zhiyao's Repositories

hkust-zhiyao/RTL-Coder
A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
Language:Python114 5 1315
hkust-zhiyao/RTLLM
An open-source benchmark for generating design RTL with natural language
Language:Verilog59 2 613
hkust-zhiyao/MasterRTL
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Language:Verilog28 3 123
hkust-zhiyao/APPLE
A circuit-element level explainer to explain machine learning model's prediction on chip layouts.
Language:Python17 1 00
hkust-zhiyao/AssertLLM
Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Language:Verilog16 1 02
hkust-zhiyao/RTL-Timer
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Language:Verilog15 2 10
hkust-zhiyao/PANDA
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
Language:Python11 2 00
hkust-zhiyao/SpecLLM
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Language:Verilog8 0 01
hkust-zhiyao/AgileDevelop
AgileDevelop&AgileTransfer: Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies
Language:Python3 1 00