Feature Request: Packed Instructions

[google0101-ryan]

On many modern or semi-modern processors, instructions are packed to save space. For example, each opcode might be 32-bits with bits 0-16 being an immediate value, or bits 16-21 being a register number. Is there any possible way to add packed instructions, for example:

load r, {v: i8} => 0b1111000000000000000rrrrrvvvvvvvv

Or something along these lines.

[gmhs022]

This can already be done to my knowledge
load {r:u6}, {v: i8} => 0b1111000000000000000 @ r @ v
You could also use subrules to assign registers to named values, like r0, r1, etc.

[google0101-ryan]

Ah, my bad. I didn't see anything from my quick scan through the documentation