instruction-set-architecture
There are 126 repositories under instruction-set-architecture topic.
hlorenzi/customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
Maratyszcza/Opcodes
Database of CPU Opcodes
zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
gabrieldim/Assembly-MIPS-Instruction-Set
Assembly program with the MIPS instruction set
edanor/umesimd
UME::SIMD A library for explicit simd vectorization.
scarv/xcrypto
XCrypto: a cryptographic ISE for RISC-V
mikeroyal/AMX-Guide
Advanced Matrix Extensions (AMX) Guide
AluVM/rust-aluvm
Rust implementation of AluVM (RISC functional machine)
kcelebi/riscv-assembler
RISC-V Assembly code assembler package for Python.
TomerAberbach/mano-simulator
🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.
sjohann81/hf-risc
HF-RISC SoC
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
scarv/scarv-cpu
SCARV: a side-channel hardened RISC-V platform
dmjio/LC3
:floppy_disk: The LC3 virtual machine
sdasgup3/parallel-processor-design
Super scalar Processor design
katamaran-project/katamaran
Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.
orbit-systems/aphelion
64-bit RISC CPU Architecture
celebi-pkg/riscv-assembler
RISC-V Assembly code assembler package for Python.
yonseicasl/Kite
Kite: Architecture Simulator for RISC-V Instruction Set
Mograsim-Team/Mograsim
Modular Graphical Simulator for Teaching Microprogramming
mannasoumya/vm-go
Stack Based Virtual Machine in Golang
wisk/isabelle
Instruction Set Architecture Description Format
arsalanyavari/mano-simulator
An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer
levindoneto/MIPS
Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.
Casparvolquardsen/Mikrorechner
Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.
Didula98/Building-a-Simple-Processor
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
farkoo/farkoo-Simulator
An assembler and hardware simulator for Mano Basic Computer, a 16-bit computer.
hohaicongthuan/RV64IF
RISC-V 64-bit with 32-bit floating point extension support.
marceldobehere/goofy-cpu
a goofy 8 bit cpu
hvudeshi/Context-Switching
Multi-Threaded Simulation of Process Switching in Operating System.
jamestiotio/compstruct
SUTD 2020 50.002 Computation Structures Code Dump
Psmths/riscal-cpu
RISCAL is a 32-bit reduced instruction-set computer (RISC) designed for learning and research purposes. It is named after my dog, Rascal.
Sacusa/MoCha
A pedagogical processor on FPGA, developed at NIIT University.
UserJHansen/Computer
Custom 32 bit computer
zsisco/yaye
yaye is Yet Another y86 Emulator