instruction-set-architecture
There are 170 repositories under instruction-set-architecture topic.
hlorenzi/customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
Maratyszcza/Opcodes
Database of CPU Opcodes
zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
mikeroyal/AMX-Guide
Advanced Matrix Extensions (AMX) Guide
gabrieldim/Assembly-MIPS-Instruction-Set
Assembly program with the MIPS instruction set
scarv/xcrypto
XCrypto: a cryptographic ISE for RISC-V
edanor/umesimd
UME::SIMD A library for explicit simd vectorization.
AluVM/aluvm
AluVM: RISC functional machine base implementation
kcelebi/riscv-assembler
RISC-V Assembly code assembler package for Python.
TomerAberbach/mano-simulator
🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.
sjohann81/hf-risc
HF-RISC SoC
aofarmakis/Nibbling-bits
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
scarv/scarv-cpu
SCARV: a side-channel hardened RISC-V platform
dmjio/LC3
:floppy_disk: The LC3 virtual machine
orbit-systems/aphelion
64-bit RISC CPU Architecture
sdasgup3/parallel-processor-design
Super scalar Processor design
ryukzak/wrench
Wrench - is a tool for educating computer architecture.
yonseicasl/Kite
Kite: Architecture Simulator for RISC-V Instruction Set
celebi-pkg/riscv-assembler
RISC-V Assembly code assembler package for Python.
katamaran-project/katamaran
Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.
HarieshAnbalagan/RV32I
Minimalistic RV32I RISC-V Processor in System Verilog
mnurczynski/pi
My very own CPU architecture! Emulator availible!
agicy/buptAsgmt-organization
北京邮电大学 2023-2024 春季学期《计算机组成原理》课程作业的相关文档
Mograsim-Team/Mograsim
Modular Graphical Simulator for Teaching Microprogramming
mannasoumya/vm-go
Stack Based Virtual Machine in Golang
Andpuv/lime-lab
LIME is an emulator of fantasy (digital) machines like those developed by community and non-community projects like fox32, OkamiStation, XrArch, Aphelion, doubleword, etc.
david-palma/mips-32bit
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.
angrysky56/MetaTransformers-Fractal-Workflow-System
This repository contains the codebase for the MetaTransformers Fractal Workflow System, a comprehensive framework for managing and orchestrating complex workflows. The system is designed to handle a wide range of data types and workflows, from simple data processing to complex AI-driven transformations.
arsalanyavari/mano-simulator
An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer
Mecca-Research/The-Binary-Decomposition-Interface
BDI - A proposed foundational computational substrate, a universal fabric designed to represent any computation.
wisk/isabelle
Instruction Set Architecture Description Format
Didula98/Building-a-Simple-Processor
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
Ecolash/RISC-Processor
𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | CS39001 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁
hohaicongthuan/RV64IF
RISC-V 64-bit with 32-bit floating point extension support.
IceWizard7/frostbyte-cpu
Assembler, ISA & everything else featuring the 16-Bit Minecraft Redstone CPU "Frostybte"