Pinned Repositories
ahb_arbiter
No description
AHB_Bus_Matrix
ahb_master
Generic AHB master stub
ahb_slave
Generic AHB slave stub
ahb_system_generator
ahb system generator
axi-bfm
AXI3 Bus Functional Models (Master & Slave)
axi_master
Generic AXI master stub
axi_slave
Generic AXI slave stub
chisel-style-guide
A Style Guide for the Chisel Hardware Construction Language
chisel-template
A template project for beginning new Chisel work
honeyxyb's Repositories
honeyxyb/axi-bfm
AXI3 Bus Functional Models (Master & Slave)
honeyxyb/chisel-style-guide
A Style Guide for the Chisel Hardware Construction Language
honeyxyb/chisel-template
A template project for beginning new Chisel work
honeyxyb/chisel-testers
Provides various testers for chisel users
honeyxyb/chisel-tutorial
chisel tutorial exercises and answers
honeyxyb/chisel3
Chisel 3
honeyxyb/chisel3-wiki
Mirror of Chisel3 Github wiki https://github.com/ucb-bar/chisel3/wiki
honeyxyb/e200_opensource
The Ultra-Low Power RISC Core
honeyxyb/Ethernet_switch_verification
Verification of Ethernet Switch System Verilog
honeyxyb/ExaSwitch
ExaNest RTL switch with AXI-stream interface
honeyxyb/IntelliJ-IDEA-Tutorial
IntelliJ IDEA 简体中文专题教程
honeyxyb/my_cs_labs
My first chisel labs.
honeyxyb/MyTSN
honeyxyb/OpenSoCFabric
OpenSoC Fabric - A Network-On-Chip Generator
honeyxyb/ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
honeyxyb/riscv-4th-workshop-tutorials
4th RISC-V Workshop Tutorials
honeyxyb/riscv-boom
Berkeley Out-of-Order Machine
honeyxyb/riscv-boom-doc
Documentation for the BOOM processor
honeyxyb/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC 6.1.0
honeyxyb/riscv-tests
honeyxyb/riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
honeyxyb/riscv-wiki
honeyxyb/riscv_vhdl
VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".
honeyxyb/rocket-chip
Rocket Chip Generator
honeyxyb/RV12
RISC-V CPU Core
honeyxyb/sifive-blocks
Common RTL blocks used in SiFive's projects
honeyxyb/translations
:panda_face: Chinese translations for classic IT resources
honeyxyb/verilog-ethernet
Verilog Ethernet components
honeyxyb/vscale
Verilog version of Z-scale
honeyxyb/zscale
Z-scale Microarchitectural Implementation of RV32 ISA