This repo contains my random experiments designing hardware.
In this project, we designed a circuit to compute the GCD of two 32-bit integers numbers. To compile and run the test, you need to either install Icarus Verilog (free) or to use Cadence Simvision (need to purchase license). The script works with both simvision and iverilog. To view the waveforms, you can use GTKWave(free) or Simvision. To run the test, first you need to clone this repository:
git clone https://github.com/hossein1387/random_hw_experiments.git
cd random_hw_experiments/GCD
Then, to compile and execute the following command:
./do_test.cmd
For Simvision only, you can add gui to command to bring up simulator:
./do_test.cmd gui
Either way, the GCDTest.sv will instantiate the designed GCD module and tests it by randomly injecting two integers. The GCDTest.sv is responsible to provide the clock and inputs for the Design Under Test (DUT). It also is responsible to verify the DUT outputs. The DUT will notify test when to pickup the output by pulling up the done bit for a clock cycle. The result of running this test will be as follow:
ncsim> run
[ 1]-GCD( 97, 532): expected= 1 actual= 1 PASS
[ 2]-GCD( 718, 114): expected= 2 actual= 2 PASS
[ 3]-GCD( 979, 862): expected= 1 actual= 1 PASS
[ 4]-GCD( 90, 65): expected= 5 actual= 5 PASS
[ 5]-GCD( 409, 134): expected= 1 actual= 1 PASS
...
[ 99]-GCD( 658, 566): expected= 2 actual= 2 PASS
[ 100]-GCD( 525, 605): expected= 5 actual= 5 PASS
Simulation complete via $finish(1) at time 600 US + 0
The output shows the expected result (generated by the test) versus the actual result (calculated by the dut).
This repo contains my experiments with Lattice iCE platform. Use the following command to synthesis your design:
make BOARD=iCE40HX8K
This will create the project for iCE40HX8K board (other option=iCEStick). It will automatically use the corresponding Physical Constraints File (pcf).
Make sure you have the follwoing tools installed:
- yosys (For synthesis)
- arachne-pnr (Place and route tool)
- icestorm (Tools for analyzing and creating bitstream files )
All Solutions licensed under MIT License. See LICENSE.txt for further details.
Copyright (c) 2017 hossein1387.