hplp/PiMulator

Issues

• Vivado using

  #19 opened 2 years ago by nedasadat-taheri
  3

• Observed one clock cycle skip while writing data to the memory

  #17 opened 2 years ago by khyatikiyawat
  2

• Implement parameterizable PiM_WIDTH

  #16 opened 3 years ago by smosanu
  0

• Observability and statistics

  #15 opened 3 years ago by smosanu
  0

• PiM templates

  #14 opened 3 years ago by smosanu
  0

• Zynq Makefile/TCL scrip missing

  #3 opened 3 years ago by smosanu
  1

• Link GUI and gem5

  #5 opened 5 years ago by smosanu
  1

• create RTL with chipyard

  #4 opened 3 years ago by ersin-cukurtas
  1

• DRAM Bank AXI Interface limited to Lite and Stream

  #2 opened 4 years ago by smosanu
  1

• Missing RD/WR buffer between I/O and internal bus for each chip

  #8 opened 4 years ago by smosanu
  2