huangjunying

huangjunying's Stars

• LL-Tools/Valkyrie

  Language:Verilog52

• lilasrahis/UNTANGLE

  UNTANGLE attack on MUX-based Locking. L. Alrahis et al., "UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction," ICCAD, 2021.

  Language:Perl32

• gatelabdavis/RANE

  Language:Verilog226

• gonsp/STIL_Interpreter

  Tool for parsing an integrated circuit test file from STIL to the particular file format of a Teradyne tester.

  Language:C++133

• KULeuven-COSIC/UnrolledBlockCiphers

  Language:VHDL92

• DfX-NYUAD/GNN-RE

  GNN-RE datasets for circuit recognition

  388

• diwu1990/uSystolic-Sim

  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

  Language:C++6614

• SNU-HPCS/CryoModel

  Language:C++153

• NYU-MLDA/OpenABC

  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

  Language:Verilog11519

• gokul-uf/fast-xnor-net

  Hopefully fast implementation of XNOR-Net in C, because, why not?

  Language:C++2612

• larq/larq

  An Open-Source Library for Training Binarized Neural Networks

  Language:Python70785

• JDAI-CV/dabnn

  dabnn is an accelerated binary neural networks inference framework for mobile platform

  Language:C++769102

• ARM-software/SCALE-Sim

  Language:Python337151

• bnna-project/bnna

  bnn accelerator

  Language:VHDL65

• Xilinx/finn

  Dataflow compiler for QNN inference on FPGAs

  Language:Python757243

• dade145/Power-analysis-approx-computing

  "DSDM2" project @ Politecnico di Milano // AY 2019-2020

  Language:Tcl11

• SureshNambi/DeBAM_Decoder_based_Approximate_Multiplier

  DeBAM : Decoder Based Approximate multiplier for Low Power Applications

  Language:Verilog53

• FreeON/spammpack

  Sparse Approximate Matrix-Matrix Multiply Package

  Language:Objective-C++43

• Ananya2/-Approximate-Computing-Techniques-for-Deep-Neural-Networks-

  Approximate computing technique is very much useful for improving efficiency (approx double) and reducing energy consumption. We will be using different adders and multipliers for this purpose and comparing their energy consumption and accuracy. And we have implemented it on Field Programmable Gate Array (FPGA) and ZEDBoard.

  Language:Verilog44

• shelljane/HEAM

  HEAM: High-Efficiency Approximate Multiplier Optimization for Deep Neural Network Accelerators

  Language:Verilog83

• Cryogenic-Computing/CryoCore

  Cryogenic Computer Modeling and Architecture Development

  11

• kunalg123/vsdflow

  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

  Language:Verilog15255

• YosysHQ/nextpnr

  nextpnr portable FPGA place and route tool

  Language:C++1.3k245

• Reconfigurable-Computing-CalPoly-Pomona/Reconfigurable-BLAST-N

  The Blastn (Basic Local Alignment Search Tool for Nucleotides) algorithm with Smith-Waterman scoring implemented for FPGAs

  Language:C7

• aidangoettsch/asg

  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.

  Language:Python213