huangjunying

-Approximate-Computing-Techniques-for-Deep-Neural-Networks-

Approximate computing technique is very much useful for improving efficiency (approx double) and reducing energy consumption. We will be using different adders and multipliers for this purpose and comparing their energy consumption and accuracy. And we have implemented it on Field Programmable Gate Array (FPGA) and ZEDBoard.

AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

accelergy

Accelergy is an energy estimation infrastructure for accelerator energy estimations

blockchain-demo

A web-based demonstration of blockchain concepts.

BNN

HLS code for a BNN accelerator

clacc

Deep Learning Accelerator (Convolution Neural Networks)

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

combinational-bnn

System Verilog code describing a fully combinational binarized neural network.

cores

Various HDL (Verilog) IP Cores

huangjunying/AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

huangjunying/accelergy

Accelergy is an energy estimation infrastructure for accelerator energy estimations

huangjunying/blockchain-demo

A web-based demonstration of blockchain concepts.

huangjunying/cores

Various HDL (Verilog) IP Cores

huangjunying/CryoCore

Cryogenic Computer Modeling and Architecture Development

huangjunying/DeBAM_Decoder_based_Approximate_Multiplier

DeBAM : Decoder Based Approximate multiplier for Low Power Applications

huangjunying/dfa-aes

C implementation of Differential Fault Analysis on AES

huangjunying/Die2Sim

Die2Sim is a tool used to aid simulations of large scale superconducting circuits. The main usage of the tool is to create JoSIM files from LEF/DEF files using an existing cell library.

huangjunying/DREAMPlace

Deep learning toolkit-enabled VLSI placement

huangjunying/f4pga

FOSS Flow For FPGA

huangjunying/finn

Dataflow compiler for QNN inference on FPGAs

huangjunying/FINN_MatrixVector_RTL

Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.github.io/FINN_MatrixVector_RTL/

huangjunying/flush-reload-attacks

huangjunying/freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

huangjunying/gdscpp

C++ library to create and read GDSII file

huangjunying/graywolf

huangjunying/larq

An Open-Source Library for Training Binarized Neural Networks

huangjunying/mitmojco

MiTMoJCo (Microscopic Tunneling Model for Josephson Contacts) is C and Python code for simulating dynamics of superconducting Josephson junctions using Werthamer's microscopic tunneling theory

huangjunying/mnist_recognition_qt

MLP written on cpp and trained on MNIST dataset.

huangjunying/Modeling_of_APUF_Compositions

Python Code and Dataset for different PUFs

huangjunying/nextpnr

nextpnr portable FPGA place and route tool

huangjunying/OpenABC

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

huangjunying/ReGDS-Logic-Gate-Extraction

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.

huangjunying/RSFQlib

RSFQ cell library

huangjunying/SCALE-Sim

huangjunying/SMTAttack

SMT Attack

huangjunying/Superconducting-Temporal-Logic

Superconducting Accelerators Design Using Temporal Logic

huangjunying/uSystolic-Sim

A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

huangjunying/XNOR-Net-PyTorch

PyTorch Implementation of XNOR-Net

huangjunying/zoo

Reference implementations of popular Binarized Neural Networks