huangjunying

-Approximate-Computing-Techniques-for-Deep-Neural-Networks-

Approximate computing technique is very much useful for improving efficiency (approx double) and reducing energy consumption. We will be using different adders and multipliers for this purpose and comparing their energy consumption and accuracy. And we have implemented it on Field Programmable Gate Array (FPGA) and ZEDBoard.

AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

accelergy

Accelergy is an energy estimation infrastructure for accelerator energy estimations

blockchain-demo

A web-based demonstration of blockchain concepts.

BNN

HLS code for a BNN accelerator

clacc

Deep Learning Accelerator (Convolution Neural Networks)

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

combinational-bnn

System Verilog code describing a fully combinational binarized neural network.

cores

Various HDL (Verilog) IP Cores

huangjunying/dabnn

dabnn is an accelerated binary neural networks inference framework for mobile platform

huangjunying/NetA

huangjunying/mult_booth_app

Approximate Booth Multiplier

huangjunying/nextpnr-lsp

huangjunying/-Approximate-Computing-Techniques-for-Deep-Neural-Networks-

Approximate computing technique is very much useful for improving efficiency (approx double) and reducing energy consumption. We will be using different adders and multipliers for this purpose and comparing their energy consumption and accuracy. And we have implemented it on Field Programmable Gate Array (FPGA) and ZEDBoard.

huangjunying/SWIFOLD

Smith-Waterman Acceleration on Intel’s FPGA with OpenCL for Long DNA Sequences

huangjunying/cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

huangjunying/BNN

HLS code for a BNN accelerator

huangjunying/combinational-bnn

System Verilog code describing a fully combinational binarized neural network.

huangjunying/SPARX

The SPARX family of lightweight block ciphers

huangjunying/clacc

Deep Learning Accelerator (Convolution Neural Networks)

huangjunying/VLSI_Processor

A series of schematics, layouts, and test files used for the construction of an 8-bit register file and ALU. The layout was completed using the open-source Magic VLSI Layout Tool, and the schematic was constructed IRSIM. Layout-versus-schematic checks were completed using IRSIM, and the transient response was simulated using HSpice.

huangjunying/XNOR-Network-operator

NO STL Version

huangjunying/spammpack

Sparse Approximate Matrix-Matrix Multiply Package

huangjunying/SimpleSmithWatermanCPP

A simple implementation of the smith-waterman algorithm (local alignment) in C++