Pinned Repositories
conv_systolic_array
(Verilog) A simple convolution layer implementation with systolic array structure
HowToCook
程序员在家做饭方法指南。Programmer's guide about how to cook at home (Chinese only).
Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
hyupupup's Repositories
hyupupup/conv_systolic_array
(Verilog) A simple convolution layer implementation with systolic array structure
hyupupup/HowToCook
程序员在家做饭方法指南。Programmer's guide about how to cook at home (Chinese only).
hyupupup/Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.