ilesser

ilesser's Stars

• jameshanlon/netlist-paths

  A library and command-line tool for querying a Verilog netlist.

  Language:C++263

• google/skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  Language:Python3k395

• mzollin/qr-vanity

  automatically embedding pixel art in QR-codes

  Language:Python588

• ydnatag/nmigen-cocotb

  cocotb extension for nMigen

  Language:Python155

• ydnatag/nmigen-yosim

  Another simulation backend for nmigen using yosys

  Language:Python41

• ngscopeclient/scopehal

  Test and measurement hardware abstraction library and protocol decodes. This is the library only. Most users should use scopehal-apps.

  Language:C++21999

• VLSIDA/OpenRAM

  An open-source static random access memory (SRAM) compiler.

  Language:Python848206

• YosysHQ/fpga-toolchain

  Multi-platform nightly builds of open source FPGA tools

  Language:C29226

• ucb-bar/chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  Language:Scala1.7k665

• ucb-bar/hammer

  Hammer: Highly Agile Masks Made Effortlessly from RTL

  Language:Python25960

• Avnet/Ultra96-PYNQ

  Board files to build Ultra 96 PYNQ image

  Language:Jupyter Notebook15151

• The-OpenROAD-Project/OpenROAD

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  Language:Verilog1.7k578

• The-OpenROAD-Project/OPENROAD_USERS_READ_ME_FIRST

  OpenROAD users should look at this repository first for instructions on getting started

  1027

• amaranth-lang/amaranth-yosys

  WebAssembly-based Yosys distribution for Amaranth HDL

  Language:Shell264

• RTimothyEdwards/qflow

  Qflow full end-to-end digital synthesis flow for ASIC designs

  Language:C19536

• zinka/arraytool

  Python based package for phased array antenna design and analysis

  Language:Python13930

• YosysHQ/sby

  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

  Language:Python41478

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.6k894

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k217

• m-labs/migen

  A Python toolbox for building complex digital hardware

  Language:Python1.2k211

• m-labs/nmigen

  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

  Language:Python66257

• drom/awesome-riscv

  😎 A curated list of awesome RISC-V implementations

  13213

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog501101

• ydnatag/sifive-bsas-hdl-python

  HDL using Python @ SiFive BsAs - Presentation material

  Language:Python4

• cr1901/miform

  Formal verification helpers for Migen

  Language:Python51

• floe/backscrub

  Virtual Video Device for Background Replacement with Deep Semantic Segmentation

  Language:C++74087

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.2k272

• Xilinx/PYNQ_Workshop

  Language:Jupyter Notebook403159

• amaranth-lang/amaranth

  A modern hardware definition language and toolchain based on Python

  Language:Python1.6k176

• kevinpt/symbolator

  HDL symbol generator

  Language:Python18649