intel/aib-phy-hardware

Issues

• mismatch between spec and model code.

  #43 opened 5 years ago by khanhpvn
  3

• synthesis

  #42 opened 5 years ago by liuzixuan1212
  2

• Typos in AIB specification 1.2

  #40 opened 5 years ago by dkehlet
  1

• Bump spreadsheet is missing Slave interface locations

  #39 opened 5 years ago by dkehlet
  1

• AIB 1.2 spec is missing Alternate (Slave) Channel Bump Map

  #38 opened 5 years ago by dkehlet
  1

• Need to identify where hardened synchronizer flops should be entered

  #35 opened 5 years ago by dkehlet
  1

• Connection device_detect and por signal in the model

  #34 opened 5 years ago by pkhanhesi
  2

• por circuit in AIB Usage Note does not work

  #36 opened 5 years ago by dkehlet
  1

• Dependencies of sideband on *adapter_rstn

  #29 opened 5 years ago by pkhanhesi
  3

• Sideband RTL defaults don't seem to match AIB Spec tables

  #30 opened 5 years ago by rbaracka
  1

• Connection issue

  #28 opened 5 years ago by pkhanhesi
  2

• Warning select out of bound on the model

  #27 opened 6 years ago by pkhanhesi
  1

• Warning SIOB on the model

  #24 opened 6 years ago by mufanvn
  1

• Connection issue when change the DATA_WIDTH on SDR mode

  #25 opened 6 years ago by pkhanhesi
  1

• MAC/PHY signal ns_mac_rdy is not connected from MAC through to the AIB bump

  #26 opened 6 years ago by dkehlet
  1

• Enhancement request: Support for emulation/FPGA

  #23 opened 6 years ago by dklowden
  3

• GDS for AIB bump locations?

  #19 opened 6 years ago by mpwalsh8
  1

• Latency mismatch with AIB specification

  #21 opened 6 years ago by pkhanhesi
  1

• Enhancement: for all channels expose the sideband shift registers

  #13 opened 6 years ago by dkehlet
  1

• Enhancement request: expose ns_mac_rdy downward from aib_top

  #12 opened 6 years ago by dkehlet
  1

• Enhancement request: use only 1 AIB signal for resetting AIB adapter

  #10 opened 6 years ago by dkehlet
  1

• Calibration AIB: Calibration Completion signals - 4 signals @ HI

  #11 opened 6 years ago by mohamadahmad
  2

• The shift register bits are not ported up in the model, therefore the user-defined bits can not be written

  #7 opened 6 years ago by sabedin01
  1

• Test ticket from the PUMA team

  #6 opened 6 years ago by dklowden
  1

• Issues Compiling for Questa (Modelsim)

  #3 opened 6 years ago by alsuchanek
  1

• dbg_test_(defines/jtagsm).v

  #2 opened 6 years ago by isaaccleffler
  2