Genesys2
Opened this issue · 3 comments
I would like to use IPBus on a Digilent Genesys2 evaluation board. It uses the same FPGA as the KC705 but would require an RGMII interface to the PHY. I can see that each of these is used by different example designs, so suspect it can't be too complicated to customise a project. Is such customisation documented or can you suggest which files I should look at to create a suitable project. I have already successfully created and built various example designs using ipbb.
Thanks
Barry Green
There's no documentation on the website for this level of customisation of the example designs, but I think you should be able to customise the design for your eval board as follows:
- Take the KC705 GMII example design as a starting point (board-specific files for that design can be found under
boards/kc705/gmii
andboards/kc705/common
) - Replace the
eth_7s_gmii
entity incomponents/kc705/gmii/firmware/hdl/kc705_gmii_infra.vhd
witheth_7s_rgmii
(source file:components/ipbus_eth/firmware/hdl/eth_7s_rgmii.vhd
) - Update the
gmii_
ports inkc705_gmii_infra.vhd
andtop_kc705_gmii.vhd
to match thergmii_
ports from corresponding files in the Enclustra AX3 PM3 design (i.e.enclustra_ax3_pm3_infra.vhd
andtop_enclustra_ax3_pm3.vhd
inboards/enclustra_ax3_pm3/synth/firmware/hdl
)kc705_gmii_infra.vhd
: lines 54 to 61 and lines 125 to 132top_kc705_gmii.vhd
: lines 45 to 52 and lines 82 to 89
- Update the pin constraints in
components/kc705/gmii/firmware/ucf/kc705_gmii.tcl
accordingly.
That said, both of these example designs were written by @dmnewbold , so he'll correct me if there's a flaw in this plan.
Tom's recipe looks OK to me. One other point is that the RGMII clock constraints for clock-data phase are 'fiddly' and sometimes require adjustment depending on board design; you can find details in the Xilinx MAC core documentation.