jblasch
BS EE grad student with focus: digital/VLSI. Interests: automated testing, digital design, HDL, ASIC, Verilog, Systemverilog, Cadence Virtuoso, Python
Portland, Oregon, U.S.A.
Pinned Repositories
Capstone___Awesome_Usage_Monitor
Senior project: Automated testing in Python for Django project
ECE428___K-L_Tool
VLSI with CAD: Python program which accepts file input and determines the minimum cutset
jblasch's Repositories
jblasch/ECE428___K-L_Tool
VLSI with CAD: Python program which accepts file input and determines the minimum cutset
jblasch/Capstone___Awesome_Usage_Monitor
Senior project: Automated testing in Python for Django project