Pinned Repositories
64-bit-Universal-Floating-Point-ISA-Compute-Engine
RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
Conscious_Gate_Transistor
Conscious Gate Transistor for creating conscious computers and machines. Provisional Patent Application with OpenSCAD 3D models.
CustomASM-for-SYMPL-ISA
SYMPL ISA Rule table for open-source CustomASM cross-assembler.
HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
IEEE-754-2008-Emulator
Universal IEEE 754-2008 Floating-Point Emulator for Xilinx and Altera FPGAs. Implements in hardware the entire (required) repertoire for half, single and double-precision binary formats, but with range limited to 5 bits and precision to 10 bits. If you require greater range and precision, contact me.
IEEE-754-2008-Fused-Multiply-Add
Fully pipelined IEEE 754-2008 "universal" Fused Multiply-Add operator in Verilog RTL directly accepts H=20 decimalCharacterSequence, binary16, binary32 and binary64 formatted numbers as operands.
IEEE-754-2008-H-20-convertFromDecimalCharacter
Fully pipelined IEEE 754-2008 H=20 "convertFromDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAs
RISC-V-SYMPL-Hybrid-Floating-Point-ISA-Compute-Engine
New hybrid ISA genetically splices the instruction pipeline of a RISC-V to the instruction pipelines of one or more SYMPL Compute Engines, giving you the best of both worlds in a single package.
SYMPL-GP-GPU-Compute-Engines
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
SYMPL_IEEE754-2019_ISA
SYMPL IEEE 754-2019 Instruction Set Architecture Compute Engine
jerry-D's Repositories
jerry-D/HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
jerry-D/SYMPL-GP-GPU-Compute-Engines
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
jerry-D/64-bit-Universal-Floating-Point-ISA-Compute-Engine
RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
jerry-D/RISC-V-SYMPL-Hybrid-Floating-Point-ISA-Compute-Engine
New hybrid ISA genetically splices the instruction pipeline of a RISC-V to the instruction pipelines of one or more SYMPL Compute Engines, giving you the best of both worlds in a single package.
jerry-D/Conscious_Gate_Transistor
Conscious Gate Transistor for creating conscious computers and machines. Provisional Patent Application with OpenSCAD 3D models.
jerry-D/SYMPL_IEEE754-2019_ISA
SYMPL IEEE 754-2019 Instruction Set Architecture Compute Engine
jerry-D/IEEE-754-2008-Fused-Multiply-Add
Fully pipelined IEEE 754-2008 "universal" Fused Multiply-Add operator in Verilog RTL directly accepts H=20 decimalCharacterSequence, binary16, binary32 and binary64 formatted numbers as operands.
jerry-D/CustomASM-for-SYMPL-ISA
SYMPL ISA Rule table for open-source CustomASM cross-assembler.
jerry-D/IEEE-754-2008-Emulator
Universal IEEE 754-2008 Floating-Point Emulator for Xilinx and Altera FPGAs. Implements in hardware the entire (required) repertoire for half, single and double-precision binary formats, but with range limited to 5 bits and precision to 10 bits. If you require greater range and precision, contact me.
jerry-D/IEEE-754-2008-H-20-convertFromDecimalCharacter
Fully pipelined IEEE 754-2008 H=20 "convertFromDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAs
jerry-D/IEEE-754-2008-H-20-convertToDecimalCharacter
Fully pipelined IEEE 754-2008 H=20 "convertToDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAs
jerry-D/IEEE-754-2008_ISA_CPU
World's first and only 64-bit IEEE 754-2008 Instruction Set Architecture CPU implements "all" mandated operations in hardware with a single instruction per operation.
jerry-D/Tek4010
Free Tektronix 4010, 4013, 4014 and 4015 terminal emulator for Raspberry Pi and Ubuntu