/riscv-cores

Repository of RISC-V architecture soft-cores written while practicing computer architecture and Verilog

Primary LanguageVerilog

RISC-V Cores

Repository of RISC-V architecture soft-cores written while practicing computer architecture and Verilog.

Content

  • RV32I-Single-Cycle: First core ever attempted. Simple single cycle single core implementing RV32I instruction set, with Harvard architecture.