jian-fang

PhD degree from TU Delft in 2019. Recent Research: Microprocessor, Heterogeneous Computer Architecture, Databases Acceleration, FPGA, NOC, RISC-V

TU DelftNetherlands

Pinned Repositories

100-Days-Of-ML-Code
100 Days of ML Coding
00
100-Days-Of-ML-Code-1
100-Days-Of-ML-Code中文版
Language:Jupyter Notebook00
a2-boot
Language:Assembly00
a2i
Language:VHDL0 1 00
a2o
Language:Verilog00
a2o-1
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
Language:Verilog0 0 00
a2p
Language:Verilog10
a2p-mpw7
A2P Core with ToySRAM memories
Language:Verilog0 0 00
ariane-wrapper
Wrapper for ETH Ariane Core
Language:Scala00
arrow
Apache Arrow is a cross-language development platform for in-memory data. It specifies a standardized language-independent columnar memory format for flat and hierarchical data, organized for efficient analytic operations on modern hardware. It also provides computational libraries and zero-copy streaming messaging and interprocess communication. Languages currently supported include C, C++, Java, JavaScript, Python, and Ruby.
Language:C++0 2 00

jian-fang's Repositories

jian-fang/a2p
Language:Verilog10
jian-fang/a2-boot
Language:Assembly00
jian-fang/a2i
Language:VHDL0 1 00
jian-fang/a2o
Language:Verilog00
jian-fang/a2o-1
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
Language:Verilog0 0 00
jian-fang/a2p-mpw7
A2P Core with ToySRAM memories
Language:Verilog0 0 00
jian-fang/ariane-wrapper
Wrapper for ETH Ariane Core
Language:Scala00
jian-fang/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
jian-fang/chisel-tutorial
chisel tutorial exercises and answers
jian-fang/chiseltest
The official testing library for Chisel circuits.
jian-fang/core-v-docs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
jian-fang/Cores-SweRV-EH2
Language:SystemVerilog1 0
jian-fang/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
jian-fang/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:SystemVerilog1 0
jian-fang/force-riscv
Instruction Set Generator initially contributed by Futurewei
jian-fang/fudian
Open source high performance IEEE-754 floating unit
jian-fang/GEM5
jian-fang/Hardware-Zstd-Compression-Unit
Language:VHDL1 0
jian-fang/HuanCun
Open-source high-performance non-blocking cache
jian-fang/microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
jian-fang/NutShell
RISC-V SoC designed by students in UCAS
Language:Scala0 0
jian-fang/openc910
OpenXuantie - OpenC910 Core
Language:Verilog1 0
jian-fang/power-fv
POWER-FV - Mirrored from OPF Git
Language:Python0 0
jian-fang/riscv-isa-sim
Spike, a RISC-V ISA Simulator
jian-fang/Searchboat
OpenPower Verification
jian-fang/toy-sram
High-specific-bandwidth memory design
jian-fang/toy-sram-mpw7
eFabless MPW-7
jian-fang/XiangShan
Open-source high-performance RISC-V processor
jian-fang/XiangShan-doc
Documentation for XiangShan
Language:TeX0 0
jian-fang/XS-Verilog-Library