jian-fang

jian-fang's Stars

• IntelLabs/riscv-vector

  Vector Acceleration IP core for RISC-V*

  Language:Scala15022

• openhwgroup/force-riscv

  Instruction Set Generator initially contributed by Futurewei

  Language:C++26658

• XUANTIE-RV/force-riscv

  Instruction Set Generator initially contributed by Futurewei

  Language:C++62

• OSCPU/NutShell

  RISC-V SoC designed by students in UCAS

  Language:Scala1.4k239

• iscas-tis/nutshell-fv

  Formal verification on NutShell using riscv-spec-core

  Language:Scala43

• riscv/riscv-aia

  Language:Makefile8119

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog965421

• riscv-software-src/riscv-isa-sim

  Spike, a RISC-V ISA Simulator

  Language:C2.4k859

• ic-lab-duth/RISC-V-Vector

  Vector processor for RISC-V vector ISA

  Language:SystemVerilog11026

• riscv-stc/riscv-matrix-project

  Top project for RISC-V Matrix extension proposal and related opensource implementations.

  234

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala4.9k663

• XUANTIE-RV/openc910

  OpenXuantie - OpenC910 Core

  Language:Verilog1.2k310

• gpgpu-sim/gpgpu-sim_distribution

  GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

  Language:C++1.1k511

• psksvp/espresso-ab-1.0

  espresso logic minimizer (https://embedded.eecs.berkeley.edu/pubs/downloads/espresso/index.htm)

  Language:C159

• chipsalliance/Cores-VeeR-EH2

  Language:SystemVerilog21558

• openhwgroup/programs

  Documentation for the OpenHW Group's set of CORE-V RISC-V cores

  Language:HTML19596

• pulp-platform/hci

  Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores

  Language:SystemVerilog1211

• pulp-platform/axi2mem

  Language:SystemVerilog56

• openhwgroup/cva6-sdk

  CVA6 SDK containing RISC-V tools and Buildroot

  Language:Makefile6267

• lowRISC/ariane

  Ariane is a 6-stage RISC-V CPU

  Language:SystemVerilog12425

• ucb-bar/cva6-wrapper

  Wrapper for ETH Ariane Core

  Language:Scala1916

• antonblanchard/simple_random

  Language:C33

• openpower-cores/a2o

  Language:Verilog13825

• openpower-cores/a2-boot

  Language:Assembly42

• openpower-cores/a2i

  Language:VHDL24437

• Xilinx/Vitis-In-Depth-Tutorial

  Language:C++11670

• inikep/lzbench

  lzbench is an in-memory benchmark of open-source LZ77/LZSS/LZMA compressors

  Language:C895182

• google/snappy

  A fast compressor/decompressor

  Language:C++6.2k981

• facebook/zstd

  Zstandard - Fast real-time compression algorithm

  Language:C23.8k2.1k

• dilawar/sesc

  Unofficial clone of SESC. Builds with modern C++ compilers.

  Language:C1710