jinzhw

jinzhw's Stars

• liangkangnan/tinyriscv

  A very simple and easy to understand RISC-V core.

  Language:C1.1k185

• richard259/serdespy

  Python library for SerDes modelling

  Language:Python5524

• WeitaoZhu/PCI_Express

  PCI_Express总线经典书籍

  1110

• brown9804/PCIe_physical_layer

  Implementation of the PCIe physical layer

  Language:Verilog2910

• mgtm98/pcie5_phy

  PCIE 5.0 Graduation project (Verification Team)

  Language:Verilog5322

• pulp-platform/iDMA

  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

  Language:SystemVerilog8927

• ishaan40/RISC-V-Processor

  A 5-stage pipelined single-core processor with support for M extension prefetching, and 2-level set-associative cache.

  Language:Verilog41

• IObundle/iob-cache

  Verilog Configurable Cache

  Language:Verilog16732

• zero-day-labs/riscv-iommu

  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

  Language:SystemVerilog7314

• freecores/1000base-x

  1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)

  Language:Verilog1615

• Mohamed-Elesaily/PCIe_specs

  Language:Verilog82

• 0xArt/RGMII_Ethernet_Transceiver_Verilog

  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY

  Language:Verilog194

• Forty-Bot/ethernet

  WIP 100BASE-TX PHY

  Language:Verilog715

• Essenceia/ethernet-physical-layer

  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

  Language:Tcl187

• stascorp/rdpwrap

  RDP Wrapper Library

  Language:Pascal14.6k3.8k

• ZihaoZhao/vcdvcd

  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

  Language:Python74

• alknvl/axis_udp

  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

  Language:Verilog3922

• jessepalomera/10G_EthernetMAC_SystemVerilog_OOP

  Final Project for my course in Advanced Verification with SystemVerilog OOP

  Language:Verilog203

• mbuesch/pyprofibus

  PROFIBUS-DP stack

  Language:Python13251

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog945416

• pulp-platform/ara

  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

  Language:C363128

• pulp-platform/pulpissimo

  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

  Language:SystemVerilog382164

• FeldmeierMichael/ProfibusVhdl

  Language:C4

• remco1271/PROFIBUS-DP

  PROFIBUS-DP Master Simulator AnyBus

  Language:C#4

• rxfx/profibusmonitor

  Language:VHDL63

• RenatoTorres/ProfibusSimulator

  Profibus capture and protocol simulator

  Language:Java95

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k680

• QuantumQuadrate/HamamatsuCameralink

  FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.

  Language:Verilog1912

• MasterPlayer/axis_register

  axi-stream output register for alternative output fifo

  Language:SystemVerilog1

• olofk/fifo

  Generic FIFO implementation with optional FWFT

  Language:Verilog5421