Pinned Repositories
CEP
Common Evaluation Platform
logic_enhanced_banyan_locking
obfuscation
A set of FIRRTL transforms for obfuscating circuits
rnn
rnn python implementation
sensitivity_attack
Sensitivity-Based Attack on Strip-Locking Circuits
SmartLock
Senior Design Project
systemConfigScript
A script to setup a mac
test
verilog2dimacs
Coverts a generic Verilog netlist into the DIMACS format compatible with many SAT solvers
verilog_benchmark_circuits
EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
jpsety's Repositories
jpsety/verilog_benchmark_circuits
EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
jpsety/verilog2dimacs
Coverts a generic Verilog netlist into the DIMACS format compatible with many SAT solvers
jpsety/sensitivity_attack
Sensitivity-Based Attack on Strip-Locking Circuits
jpsety/CEP
Common Evaluation Platform
jpsety/logic_enhanced_banyan_locking
jpsety/obfuscation
A set of FIRRTL transforms for obfuscating circuits
jpsety/rnn
rnn python implementation
jpsety/SmartLock
Senior Design Project
jpsety/systemConfigScript
A script to setup a mac
jpsety/test