jracevedob's Stars
jracevedob/MPSoC_Networking
This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)
jracevedob/cloud-security-xsuaa-integration
Integration libraries and samples for authenticating users and clients bound to XSUAA authentication and authorization service or identity authentication service.
NVIDIA/5t5g
This project shows how to leverage your DPDK network application with Mellanox 5T5G features like Accurate Send Scheduling and eCPRI flow steering rules
CloudNativeDataPlane/cndp
Cloud Native Data Plane (CNDP) is a collection of user space libraries to accelerate packet processing for cloud applications using AF_XDP sockets as the primary I/O..
contiki-ng/contiki-ng
Contiki-NG: The OS for Next Generation IoT Devices
magma/magma
Platform for building access networks and modular network services
pulp-platform/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
fpgadeveloper/zcu102-ethernet
Design for using Ethernet on the ZCU102 development board
RADAR-base/RADAR-IoT
RADAR-base IoT framework
nsg-ethz/p4-learning
Compilation of P4 exercises, examples, documentation, slides for learning or teaching
Xilinx/wireless-apps
Software, BSPs etc. for 5G wireless IP and PetaLinux
stevelorenz/programming-playground
Practice makes one a master.
michel-steuwer/phd-thesis
TeX source of my PhD thesis
Orange-OpenSource/towards5gs-helm
Helm charts for deploying 5G network services on Kubernetes
elevate-lang/elevate
The implementation of the Elevate language
gallenmu/MoonGen
MoonGen is a fully scriptable high-speed packet generator build on DPDK and LuaJIT. It can saturate a 10 GbE connection with 64 byte packets on a single CPU core while executing user-provided Lua scripts for each packet.
rougier/CPP-Crash-Course
C++ Crash Course
stevelorenz/build-vnf
:coffee: Experimental/research project to build high-performance and energy-efficient virtual network functions (VNFs).
TrainingByPackt/CPP-Data-Structures-and-Algorithm-Design-Principles
Leverage the power of modern C++ to build robust and scalable applications
panr/icon2code
Figma plugin for generating JSON from icons set
maiconkist/gr-hydra
HyDRA source code
jracevedob/Processor-Design
In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.
Xilinx/RFNoC-HLS-ATSC-RX
classicthesis/classicthesis
(old) fork of André Miede's LaTeX classicthesis template, see bitbucket for current version
Xilinx/meta-xilinx
Collection of Yocto Project layers to enable AMD Xilinx products
ytmytm/c64-bitcoin-miner
C64 Bitcoin miner