jrrk

Pinned Repositories

axi_mem_if
Simple single-port AXI memory interface
Language:SystemVerilog10
cbzone
Port of the classic BattleZone arcade game to LowRISC
Language:C2 4 01
debian-riscv64
Language:Shell1 3 06
efuns
efuns is a re-write of emacs in ocaml written by Fabrice Le Fessant
Language:OCaml2 3 00
ethernet_mac
Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
Language:VHDL10
LEF
Mirror of Cadence's LEF parser library (https://openeda.si2.org/projects/lefdefnew/)
Language:C++3 4 04
ocaml-for-ios
Automatically exported from code.google.com/p/ocaml-for-ios
Language:OCaml1 2 40
sysver2ver
Converting System Verilog to plain Verilog using .xml dump from Verilator
Language:Verilog6 5 11
u-boot-riscv
Port of u-boot to RISCV based ariane core
Language:C6 3 14
verilog-parser-ocaml
Automatically exported from code.google.com/p/verilog-parser-ocaml
Language:Verilog31

jrrk's Repositories

jrrk/sysver2ver
Converting System Verilog to plain Verilog using .xml dump from Verilator
Language:Verilog6 5 11
jrrk/cbzone
Port of the classic BattleZone arcade game to LowRISC
Language:C2 4 01
jrrk/spi_mem_programmer
A simple verilog module for programming (Q)SPI flash memories.
Language:SystemVerilog1
jrrk/apb_uart
Language:VHDL
jrrk/ariane
Ariane is a 6-stage RISC-V CPU
Language:SystemVerilog4 101
jrrk/axi
AXI4 and AXI4-Lite interface definitions and testbench utilities
Language:SystemVerilog3 0
jrrk/blktests
Linux kernel block layer testing framework
Language:Shell
jrrk/buildroot
Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
jrrk/cooltaxtool
UK Tax Calculator & Visualiser
jrrk/firrtl_grammar
Learning about firrtl grammar
Language:OCaml
jrrk/fpnew
[UNRELEASED] Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Language:VHDL
jrrk/GOCR
An OS X project that holds a simple framework for the GOCR ( http://jocr.sourceforge.net)
jrrk/ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
Language:SystemVerilog
jrrk/lowrisc-bbl
Language:C
jrrk/NEMU
jrrk/nexus-am
jrrk/nuttx
Apache NuttX is a mature, real-time embedded operating system (RTOS)
jrrk/openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
jrrk/Posit-HDL-Arithmetic
Universal number Posit HDL Arithmetic Architecture generator
Language:Verilog
jrrk/riscv-dbg
RISC-V Debug Support for our PULP Cores
Language:SystemVerilog
jrrk/riscv-gnu-toolchain-1
GNU toolchain for RISC-V, including GCC
Language:C
jrrk/riscv_vhdl
VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".
Language:Verilog
jrrk/rv_plic
Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)
Language:SystemVerilog2 0
jrrk/sdram-controller
Verilog SDRAM memory controller
Language:Verilog
jrrk/SDRAM-Controller-1
SDRAM Controller
jrrk/TestRIG
Testing processors with Random Instruction Generation
Language:Haskell
jrrk/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Language:C
jrrk/xap-gcc
GCC for XAP
jrrk/XiangShan
Open-source high-performance RISC-V processor
jrrk/Xilinx_Readback_Verify
A simple tool for verifying readback data for Xilinx Virtex 5 and 7-series devices
Language:C++