lowRISC

Developing the Silicon Commons

Pinned Repositories

ariane
Ariane is a 6-stage RISC-V CPU
Language:SystemVerilog144 14 027
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Language:SystemVerilog1.6k 105 872647
ibex-demo-system
A demo system for Ibex including debug support and some peripherals
Language:C76 15 4162
lowrisc-chip
The root repo for lowRISC project and FPGA demos.
Language:SystemVerilog602 59 131149
lowrisc-fpga
Untethered (stand-alone) FPGA implementation of the lowRISC SoC
Language:C56 15 616
lowrisc-toolchains
UNSUPPORTED INTERNAL toolchain builds
Language:Shell45 15 2019
muntjac
64-bit multicore Linux-capable RISC-V processor
Language:SystemVerilog97 11 112
opentitan
OpenTitan: Open source silicon root of trust
Language:SystemVerilog3k 113 7.4k893
riscv-llvm
RISC-V support for LLVM projects (LLVM, Clang, ...)
Language:Shell273 29 6355
style-guides
lowRISC Style Guides
453 69 34125

lowRISC's Repositories

lowRISC/opentitan
OpenTitan: Open source silicon root of trust
Language:SystemVerilog3k 113 7.4k893
lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Language:SystemVerilog1.6k 105 872647
lowRISC/style-guides
lowRISC Style Guides
453 69 34125
lowRISC/muntjac
64-bit multicore Linux-capable RISC-V processor
Language:SystemVerilog97 11 112
lowRISC/ibex-demo-system
A demo system for Ibex including debug support and some peripherals
Language:C76 15 4162
lowRISC/lowrisc-toolchains
UNSUPPORTED INTERNAL toolchain builds
Language:Shell45 15 2019
lowRISC/sonata-system
A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
Language:C++45 11 6226
lowRISC/ot-sca
Side-channel analysis setup for OpenTitan
Language:Jupyter Notebook36 13 8630
lowRISC/riscv-isa-sim
RISC-V Functional ISA Simulator
Language:C17 9 010
lowRISC/sunburst-chip
An open silicon CHERIoT Ibex microcontroller chip
Language:C154
lowRISC/container-hotplug
Hot-plug devices into a Docker container as they are plugged.
Language:Rust13 12 55
lowRISC/sonata-software
Software, build flows and examples for the Sonata System
Language:C++12 13 713
lowRISC/opentitan-provisioning
Reference OpenTitan Provisioning Infrastructure
Language:Go9 10 348
lowRISC/crt
Compiler Repository Toolkit
Language:Starlark7 5 215
lowRISC/lowrisc-nix
lowRISC Nix Packages and Environments
Language:Nix7 10 58
lowRISC/qemu
Fork of QEMU for development of lowRISC platforms (including OpenTitan)
Language:C4 3 2311
lowRISC/dvsim
DVSim is a build and run system written in Python that runs a variety of EDA tool flows
Language:Python21
lowRISC/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.
Language:C++2 1 06
lowRISC/cheriot-ibex
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
Language:SystemVerilog1 1 03
lowRISC/cheriot-rtos
The RTOS components for the CHERIoT research platform
Language:C++1 0 05
lowRISC/cheriot-sail
Sail code model of the CHERIoT ISA
Language:TeX1 0 01
lowRISC/parallel-cp
A tiny parallel file copy utility
Language:Rust1
lowRISC/part-number-registry
Registry of various part number and ID namespaces that lowRISC controls
1
lowRISC/TestRIG
Testing processors with Random Instruction Generation
Language:Python1 1 02
lowRISC/benevisrdl
This repository houses PeakRDL plugins, named after Ben Nevis, the UK's tallest peak.
Language:SystemVerilog1
lowRISC/QuickCheckVEngine
A RISC-V TestRIG Verification Engine based on QuickCheck
Language:Haskell1 01
lowRISC/rules_python
Bazel Python Rules
Language:Starlark2 02
lowRISC/sail
Sail architecture definition language
Language:Isabelle0 0
lowRISC/sail-riscv
Sail RISC-V model
Language:Coq0 01
lowRISC/verilator
Verilator open-source SystemVerilog simulator and lint system