lowRISC/riscv-llvm

Issues

• Add support for RV32IM without division

  #45 opened 7 years ago by luismarques
  4

• How to build lli (LLVM JIT) for RISCV?

  #70 opened 3 years ago by Joejiong
  1

• New rebase?

  #69 opened 4 years ago by JL2210
  0

• Add a new mcpu=C910 in llvm-mc

  #68 opened 4 years ago by WilliamWangPeng
  0

• Implement and test support for all RISC-V inline asm constraints

  #25 opened 7 years ago by asb
  3

• RISC-V ISA for E mode

  #67 opened 5 years ago by WonHoYoo
  0

• riscv64 crashes on global variable access

  #65 opened 6 years ago by Lichtso
  2

• How to add RVE to the LLVM

  #64 opened 6 years ago by liang1232018
  1

• Updates to README.md regarding baremetal.patch

  #63 opened 6 years ago by colematt
  1

• file in wrong format

  #61 opened 6 years ago by aguilarmg
  2

• RISCV LLVM benchmark

  #62 opened 6 years ago by zejiang0jason
  0

• Function calls returning double may generate invalid code

  #54 opened 6 years ago by luporl
  1

• target triple parsing

  #60 opened 6 years ago by nburow2
  1

• Exception handling support

  #59 opened 6 years ago by luismarques
  4

• Debug info is wrong when rustc expects a function to be inlined but llvm doesn't inline it

  #58 opened 6 years ago by dvc94ch
  1

• disassembly printing

  #57 opened 6 years ago
  1

• state of atomic support

  #56 opened 7 years ago by dvc94ch
  2

• Support TLS

  #44 opened 7 years ago by luismarques
  4

• Further investigate performance differences vs riscv-gcc

  #53 opened 7 years ago by asb
  1

• __builtin_flt_rounds() crashes on riscv64

  #52 opened 7 years ago by EdSchouten
  0

• Definition of __(U)INT64_TYPE__ on riscv64 is inconsistent with other targets

  #51 opened 7 years ago by EdSchouten
  1

• Clang for RISC-V 32/64 bits crashes on __c11_atomic_*_fence() with variable memory order

  #49 opened 7 years ago by EdSchouten
  0

• Ensure proper call frame information metadata is set

  #43 opened 7 years ago by asb
  10

• Release build fails

  #48 opened 7 years ago by PkmX
  1

• Implement frame pointer elimination

  #41 opened 7 years ago by asb
  1

• RV64 support

  #20 opened 7 years ago by asb
  1

• Simplify ABI lowering requirements for frontends

  #40 opened 7 years ago by asb
  1

• Implement branch analysis

  #24 opened 7 years ago by asb
  1

• Support all RISC-V assembler pseudoinstructions

  #30 opened 7 years ago by asb
  1

• Teach the assembler to recognise standard CSR names

  #36 opened 7 years ago by asb
  2

• Make decision on splitting instruction definitions from patterns

  #42 opened 7 years ago by asb
  2

• Assembler mnemonics spellchecker

  #39 opened 7 years ago by asb
  0

• Improve diagnostics for invalid register names

  #38 opened 7 years ago by asb
  0

• Investigate options for adding support for the GCC torture suite to the LLVM test suite

  #37 opened 7 years ago by asb
  0

• Shrinkwrap support

  #35 opened 7 years ago by asb
  0

• Improve code quality for multiplication by a constant

  #34 opened 7 years ago by asb
  0

• Jump table support

  #33 opened 7 years ago by asb
  0

• Support for FDPIC/ROPI/RWPI (PIC on embedded platforms)

  #32 opened 7 years ago by asb
  0

• Support for lowRISC tagged memory

  #31 opened 7 years ago by asb
  0

• compiler-rt RISC-V port

  #17 opened 7 years ago by asb
  0

• Improve code quality for loads/stores to globals

  #29 opened 7 years ago by asb
  0

• Improve code quality for large stack adjustments

  #28 opened 7 years ago by asb
  0

• Machine scheduling model for at least one core (e.g. Rocket, PULP)

  #27 opened 7 years ago by asb
  0

• Support for PIC, and other code models

  #26 opened 7 years ago by asb
  0

• RV32E support

  #23 opened 7 years ago by asb
  0

• Compressed ('C') instruction set MC-layer support

  #22 opened 7 years ago by asb
  0

• Compressed ('C') instruction set codegen/optimisation support

  #21 opened 7 years ago by asb
  0

• GlobalISel support

  #19 opened 7 years ago by asb
  0

• LLDB RISC-V port

  #18 opened 7 years ago by asb
  0

• LLD RISC-V support

  #16 opened 7 years ago by asb
  0