Pinned Repositories
async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
binutils-or1k
binutils with cleaned up OpenRISC port based on CGEN-based opcodes and gas libraries
cgen
CGEN
mor1kx
mor1kx
mor1kx-dev-env
Development and verification environment for the mor1kx core
or1ktrace
Disassembly and execution trace generation library for OpenRISC 1000 models
orpsoc
OpenRISC Reference Platform System-On-Chip
orpsoc-cores
Core description files for ORPSoCv3
sifive-blocks
Common RTL blocks used in SiFive's projects
juliusbaxter's Repositories
juliusbaxter/mor1kx-dev-env
Development and verification environment for the mor1kx core
juliusbaxter/mor1kx
mor1kx
juliusbaxter/cgen
CGEN
juliusbaxter/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
juliusbaxter/binutils-or1k
binutils with cleaned up OpenRISC port based on CGEN-based opcodes and gas libraries
juliusbaxter/or1ktrace
Disassembly and execution trace generation library for OpenRISC 1000 models
juliusbaxter/orpsoc
OpenRISC Reference Platform System-On-Chip
juliusbaxter/orpsoc-cores
Core description files for ORPSoCv3
juliusbaxter/sifive-blocks
Common RTL blocks used in SiFive's projects
juliusbaxter/freedom
Source files for SiFive's Freedom platforms
juliusbaxter/orconf2013
juliusbaxter/SaleaeSDIOAnalyzer
SDIO Analyzer for Saleae Logic