kangjian888

KANG JIAN got his bachelor's degree in Huazhong University of Sci & Tech in 2017. Now he is pursuing his PhD degree in Hong Kong University of Sci & Tech.

Hong Kong University of Science and TechnologyHong Kong

Pinned Repositories

attached_img
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axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Language:SystemVerilog00
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:Scala00
codeform
This is my software course desing during my undergranduate period.
Language:C++00
color_filter_testing
Language:SystemVerilog00
DMT-for-VLC-FPGA
This is the project of VLC transmitter employing DMT with bit and energy allocation
Language:Verilog11
DMT-for-VLC-MATLAB
Simulation of OFDM VLC with bit and energy allocation
Language:MATLAB5 1 02
PAM4-RGB-FPGA
Language:SystemVerilog2 0 00
VLC_OFDM_Simulation
Language:MATLAB7 1 02
VLC_OFDM_Simulation_original
This is original version.
Language:MATLAB4 1 03

kangjian888's Repositories

kangjian888/VLC_OFDM_Simulation
Language:MATLAB7 1 02
kangjian888/DMT-for-VLC-MATLAB
Simulation of OFDM VLC with bit and energy allocation
Language:MATLAB5 1 02
kangjian888/VLC_OFDM_Simulation_original
This is original version.
Language:MATLAB4 1 03
kangjian888/PAM4-RGB-FPGA
Language:SystemVerilog2 0 00
kangjian888/DMT-for-VLC-FPGA
This is the project of VLC transmitter employing DMT with bit and energy allocation
Language:Verilog11
kangjian888/attached_img
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kangjian888/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Language:SystemVerilog00
kangjian888/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:Scala00
kangjian888/color_filter_testing
Language:SystemVerilog00
kangjian888/common_ips
This is some common ips used in digital circuit design
Language:SystemVerilog1 0
kangjian888/Digital-System-Design-and-Generation
Digital System Design and Generation - System Verilog Projects
Language:Verilog1 0
kangjian888/Ethernet_test_Alinx2Aritix-7
This is the project modified from the AX516 Ethernet test demo transplant to Artix-7 developing board
Language:VHDL
kangjian888/FIR_FILTER
THE COURSE PROJECT OF VLSI
Language:Verilog
kangjian888/FlooNoC
A Fast, Low-Overhead On-chip Network
Language:SystemVerilog0 0
kangjian888/homepage
Language:HTML
kangjian888/Light_OFDM_Modulation
Language:Matlab
kangjian888/Operating_system_on_ONetSwitch20
plant Linux system on ONetSwitch20 and make the system support the network switches
Language:Verilog
kangjian888/practicalAI
📚 A practical approach to learning and using machine learning.
Language:Jupyter Notebook1 0
kangjian888/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
kangjian888/python_experiment
for python and ml learning
Language:Python
kangjian888/u-boot-xlnx
The official Xilinx u-boot repository
Language:C
kangjian888/uart
Language:Verilog
kangjian888/Underwater_OOK
Language:C
kangjian888/verilog_everyday
the result of verilog everyday activity
Language:Verilog1
kangjian888/verilog_everyday_prj
simulation project file and result
Language:Objective-C
kangjian888/video_trans_advanced
This is the second version of video transmission project using 1000Mbps Ethernet and GTP(500Mbps) as serial port.
Language:VHDL
kangjian888/video_trans_pro
This is the first version of video transmission project. 100Mbps Ethernet Port and UART serial port(4Mpbs)
Language:VHDL
kangjian888/video_trans_sourcecode
Language:VHDL
kangjian888/vlsi_project
The template for VLSI project
Language:Verilog
kangjian888/WORK_PROCESS
This is the work summary of Jimmy
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