this is actually is a very simple divider circuit. We used clock generation IP provided by Xilinx. You need used Vivado 2018.3 to open and modify the project. The path of main project is /proj/color_filter_testing/color_filter_testing.xpr The ip management project is /ips/managed_ip_project/managed_ip_project.xpr
If you want to change the output frequency, just change the parameter of clock ip.