krsheshu's Stars
vyomasystems-lab/challenges-krsheshu
challenges-krsheshu created by GitHub Classroom
freecores/fpga-median
FPGA-based Median Filter
avashist003/SystemVerilog_Design_Verification
Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
raysalemi/uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
raulbehl/100DaysOfRTL
100 Days of RTL
krsheshu/hls_libs
HLS Implementation of various libraries for Vivado
lastweek/fpga_readings
Recipe for FPGA cooking
KastnerRG/pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
krsheshu/python_libs
Reference implementation for python libs
krsheshu/best_practices
Best design Practices for a variety of Use Cases
krsheshu/fpga_libs
A collection of reusable fpga modules
krsheshu/luttappi
A project for fpga implementation of neural networks
tensorflow/tensorflow
An Open Source Machine Learning Framework for Everyone
cfelton/pyFDA
Python Filter Design Analysis Tool
cfelton/filter-blocks
A collection of digital hardware filters implemented in myhdl
wnew/hdl_library
A library of verilog and vhdl modules
devbisme/myhdl-resources
A collection of awesome MyHDL tutorials, projects and third-party tools.
cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
cfelton/rhea
A collection of MyHDL cores and tools for complex digital circuit design
myhdl/myhdl
The MyHDL development repository