/SystemVerilog_Design_Verification

Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog

Primary LanguageSystemVerilogMIT LicenseMIT

SystemVerilog Design & Verification

The designs are linked to my blog that explains many techniques on how to write good RTL Blog Link.

In this repository I include various RTL designs using SystemVerilog HDL. Futher, I build verification environment using Yosys formal suite along with the simulation based testbench. This will follow my #100DaysofRTL challenge on LinkedIn.

Each of the design blocks contain their own separate documention.

  • This repository is continuously maintained and updated. When you fork, make sure to pull frequently.